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target/arm: [tcg,a64] Port to init_disas_context

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Incrementally paves the way towards using the generic instruction translation
loop.

Backports commit 5c03990665aa9095e4d2734c8ca0f936a8e8f000 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-04 19:15:22 -05:00 committed by Lioncash
parent 5e5c722359
commit 529c6c17f1
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 27 additions and 16 deletions
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43
qemu/target/arm/translate-a64.c
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@ -11444,24 +11444,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s); free_tmp_a64(s);
} }
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
TranslationBlock *tb) CPUState *cpu, int max_insns)
{ {
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext *dc = container_of(dcbase, DisasContext, base); DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong next_page_start; CPUARMState *env = cpu->env_ptr;
int max_insns; ARMCPU *arm_cpu = arm_env_get_cpu(env);
TCGContext *tcg_ctx = env->uc->tcg_ctx;
bool block_full = false;
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
// Unicorn: Store uc context
dc->uc = env->uc; dc->uc = env->uc;
dc->pc = dc->base.pc_first; dc->pc = dc->base.pc_first;
@ -11488,7 +11478,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
dc->vec_len = 0; dc->vec_len = 0;
dc->vec_stride = 0; dc->vec_stride = 0;
dc->cp_regs = cpu->cp_regs; dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features; dc->features = env->features;
/* Single step state. The code-generation logic here is: /* Single step state. The code-generation logic here is:
@ -11513,6 +11503,26 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
init_tmp_a64_array(dc); init_tmp_a64_array(dc);
return max_insns;
}
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
TranslationBlock *tb)
{
CPUARMState *env = cs->env_ptr;
TCGContext *tcg_ctx = env->uc->tcg_ctx;
DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong next_page_start;
int max_insns;
bool block_full = false;
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
max_insns = dc->base.tb->cflags & CF_COUNT_MASK; max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) { if (max_insns == 0) {
@ -11521,6 +11531,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
if (max_insns > TCG_MAX_INSNS) { if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS; max_insns = TCG_MAX_INSNS;
} }
max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
tcg_clear_temp_count(); tcg_clear_temp_count();