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Implemented read and write access to the YMM registers (#819)

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Samuel Groß 2017-05-05 03:02:58 +02:00 committed by Nguyen Anh Quynh
parent 4a62409949
commit 5385baba39
2 changed files with 57 additions and 0 deletions
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21
bindings/python/unicorn/unicorn.py
View file

@ -223,6 +223,15 @@ class uc_x86_xmm(ctypes.Structure):
("high_qword", ctypes.c_uint64), ("high_qword", ctypes.c_uint64),
] ]
class uc_x86_ymm(ctypes.Structure):
"""256-bit ymm register"""
_fields_ = [
("first_qword", ctypes.c_uint64),
("second_qword", ctypes.c_uint64),
("third_qword", ctypes.c_uint64),
("fourth_qword", ctypes.c_uint64),
]
class uc_arm64_neon128(ctypes.Structure): class uc_arm64_neon128(ctypes.Structure):
"""128-bit neon register""" """128-bit neon register"""
_fields_ = [ _fields_ = [
@ -314,6 +323,12 @@ class Uc(object):
if status != uc.UC_ERR_OK: if status != uc.UC_ERR_OK:
raise UcError(status) raise UcError(status)
return reg.low_qword | (reg.high_qword << 64) return reg.low_qword | (reg.high_qword << 64)
if reg_id in range(x86_const.UC_X86_REG_YMM0, x86_const.UC_X86_REG_YMM0+8):
reg = uc_x86_ymm()
status = _uc.uc_reg_read(self._uch, reg_id, ctypes.byref(reg))
if status != uc.UC_ERR_OK:
raise UcError(status)
return reg.first_qword | (reg.second_qword << 64) | (reg.third_qword << 128) | (reg.fourth_qword << 192)
if reg_id is x86_const.UC_X86_REG_MSR: if reg_id is x86_const.UC_X86_REG_MSR:
if opt is None: if opt is None:
raise UcError(uc.UC_ERR_ARG) raise UcError(uc.UC_ERR_ARG)
@ -359,6 +374,12 @@ class Uc(object):
reg = uc_x86_xmm() reg = uc_x86_xmm()
reg.low_qword = value & 0xffffffffffffffff reg.low_qword = value & 0xffffffffffffffff
reg.high_qword = value >> 64 reg.high_qword = value >> 64
if reg_id in range(x86_const.UC_X86_REG_YMM0, x86_const.UC_X86_REG_YMM0+8):
reg = uc_x86_ymm()
reg.first_qword = value & 0xffffffffffffffff
reg.second_qword = (value >> 64) & 0xffffffffffffffff
reg.third_qword = (value >> 128) & 0xffffffffffffffff
reg.fourth_qword = value >> 192
if reg_id is x86_const.UC_X86_REG_MSR: if reg_id is x86_const.UC_X86_REG_MSR:
reg = uc_x86_msr() reg = uc_x86_msr()
reg.rid = value[0] reg.rid = value[0]

36
qemu/target-i386/unicorn.c
View file

@ -283,6 +283,24 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
dst[1] = reg->_d[1]; dst[1] = reg->_d[1];
continue; continue;
} }
case UC_X86_REG_YMM0:
case UC_X86_REG_YMM1:
case UC_X86_REG_YMM2:
case UC_X86_REG_YMM3:
case UC_X86_REG_YMM4:
case UC_X86_REG_YMM5:
case UC_X86_REG_YMM6:
case UC_X86_REG_YMM7:
{
float64 *dst = (float64*)value;
XMMReg *lo_reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_YMM0];
XMMReg *hi_reg = &X86_CPU(uc, mycpu)->env.ymmh_regs[regid - UC_X86_REG_YMM0];
dst[0] = lo_reg->_d[0];
dst[1] = lo_reg->_d[1];
dst[2] = hi_reg->_d[0];
dst[3] = hi_reg->_d[1];
continue;
}
} }
switch(uc->mode) { switch(uc->mode) {
@ -804,6 +822,24 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
reg->_d[1] = src[1]; reg->_d[1] = src[1];
continue; continue;
} }
case UC_X86_REG_YMM0:
case UC_X86_REG_YMM1:
case UC_X86_REG_YMM2:
case UC_X86_REG_YMM3:
case UC_X86_REG_YMM4:
case UC_X86_REG_YMM5:
case UC_X86_REG_YMM6:
case UC_X86_REG_YMM7:
{
float64 *src = (float64*)value;
XMMReg *lo_reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_YMM0];
XMMReg *hi_reg = &X86_CPU(uc, mycpu)->env.ymmh_regs[regid - UC_X86_REG_YMM0];
lo_reg->_d[0] = src[0];
lo_reg->_d[1] = src[1];
hi_reg->_d[0] = src[2];
hi_reg->_d[1] = src[3];
continue;
}
} }
switch(uc->mode) { switch(uc->mode) {