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tcg: Make probe_write() return a pointer to the host page

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... similar to tlb_vaddr_to_host(); however, allow access to the host
page except when TLB_NOTDIRTY or TLB_MMIO is set.

Backports commit fef39ccd567032d3ad520ed80f3576068e6eb2e3 from qemu
This commit is contained in:
David Hildenbrand 2020-01-14 07:04:15 -05:00 committed by Lioncash
parent 2bc3843fe3
commit 53c3c47efa
2 changed files with 18 additions and 7 deletions
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19
qemu/accel/tcg/cputlb.c
View file

@ -706,10 +706,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
/* Probe for whether the specified guest write access is permitted. /* Probe for whether the specified guest write access is permitted.
* If it is not permitted then an exception will be taken in the same * If it is not permitted then an exception will be taken in the same
* way as if this were a real write access (and we will not return). * way as if this were a real write access (and we will not return).
* Otherwise the function will return, and there will be a valid * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
* entry in the TLB for this access. * returns the address of the host page similar to tlb_vaddr_to_host().
*/ */
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr) uintptr_t retaddr)
{ {
uintptr_t index = tlb_index(env, mmu_idx, addr); uintptr_t index = tlb_index(env, mmu_idx, addr);
@ -729,12 +729,23 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
tlb_addr = tlb_addr_write(entry); tlb_addr = tlb_addr_write(entry);
} }
if (!size) {
return NULL;
}
/* Handle watchpoints. */ /* Handle watchpoints. */
if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { if (tlb_addr & TLB_WATCHPOINT) {
cpu_check_watchpoint(env_cpu(env), addr, size, cpu_check_watchpoint(env_cpu(env), addr, size,
env->iotlb[mmu_idx][index].attrs, env->iotlb[mmu_idx][index].attrs,
BP_MEM_WRITE, retaddr); BP_MEM_WRITE, retaddr);
} }
if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) {
/* I/O access */
return NULL;
}
return (void *)((uintptr_t)addr + entry->addend);
} }
void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,

2
qemu/include/exec/exec-all.h
View file

@ -213,7 +213,7 @@ static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
} }
#endif #endif
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr); uintptr_t retaddr);
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */