mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-03-27 13:45:07 +00:00
target-m68k: Inline addx, subx, negx
And add opcodes for 680x0 Backports commit a665a820e5d46b1611f409fbc7a540fe1c6bf5c8 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
b796f934ff
commit
549e31cc72
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@ -191,46 +191,6 @@ uint32_t HELPER(sats)(uint32_t val, uint32_t v)
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return val;
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}
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uint32_t HELPER(subx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2)
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{
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uint32_t res, new_x;
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if (env->cc_x) {
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new_x = (op1 <= op2);
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res = op1 - (op2 + 1);
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} else {
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new_x = (op1 < op2);
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res = op1 - op2;
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}
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env->cc_x = new_x;
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env->cc_c = new_x;
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env->cc_n = res;
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env->cc_z |= res; /* !Z is sticky */
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env->cc_v = (res ^ op1) & (op1 ^ op2);
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return res;
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}
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uint32_t HELPER(addx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2)
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{
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uint32_t res, new_x;
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if (env->cc_x) {
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res = op1 + op2 + 1;
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new_x = (res <= op2);
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} else {
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res = op1 + op2;
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new_x = (res < op2);
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}
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env->cc_x = new_x;
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env->cc_c = new_x;
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env->cc_n = res;
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env->cc_z |= res; /* !Z is sticky. */
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env->cc_v = (res ^ op1) & ~(op1 ^ op2);
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return res;
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}
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void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
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{
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env->sr = val & 0xffe0;
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@ -5,8 +5,6 @@ DEF_HELPER_1(ff1, i32, i32)
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DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_2(divu, void, env, i32)
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DEF_HELPER_2(divs, void, env, i32)
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DEF_HELPER_3(addx_cc, i32, env, i32, i32)
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DEF_HELPER_3(subx_cc, i32, env, i32, i32)
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DEF_HELPER_3(shl_cc, i32, env, i32, i32)
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DEF_HELPER_3(shr_cc, i32, env, i32, i32)
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DEF_HELPER_3(sar_cc, i32, env, i32, i32)
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@ -1553,11 +1553,50 @@ DISAS_INSN(move)
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DISAS_INSN(negx)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv reg;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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gen_flush_flags(s);
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reg = DREG(insn, 0);
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gen_helper_subx_cc(tcg_ctx, reg, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, 0), reg);
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TCGv z;
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TCGv src;
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TCGv addr;
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int opsize;
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opsize = insn_opsize(insn);
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SRC_EA(env, src, opsize, 1, &addr);
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gen_flush_flags(s); /* compute old Z */
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/* Perform substract with borrow.
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* (X, N) = -(src + X);
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*/
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z = tcg_const_i32(tcg_ctx, 0);
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tcg_gen_add2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
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tcg_gen_sub2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
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tcg_temp_free(tcg_ctx, z);
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gen_ext(s, QREG_CC_N, QREG_CC_N, opsize, 1);
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tcg_gen_andi_i32(tcg_ctx, QREG_CC_X, QREG_CC_X, 1);
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/* Compute signed-overflow for negation. The normal formula for
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* subtraction is (res ^ src) & (src ^ dest), but with dest==0
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* this simplies to res & src.
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*/
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tcg_gen_and_i32(tcg_ctx, QREG_CC_V, QREG_CC_N, src);
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/* Copy the rest of the results into place. */
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tcg_gen_or_i32(tcg_ctx, QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_C, QREG_CC_X);
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set_cc_op(s, CC_OP_FLAGS);
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/* result is in QREG_CC_N */
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DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
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}
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DISAS_INSN(lea)
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@ -2015,16 +2054,83 @@ DISAS_INSN(suba)
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tcg_gen_sub_i32(tcg_ctx, reg, reg, src);
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}
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DISAS_INSN(subx)
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static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv reg;
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TCGv src;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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TCGv tmp;
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gen_flush_flags(s);
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reg = DREG(insn, 9);
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src = DREG(insn, 0);
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gen_helper_subx_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, src);
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gen_flush_flags(s); /* compute old Z */
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/* Perform substract with borrow.
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* (X, N) = dest - (src + X);
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*/
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tmp = tcg_const_i32(tcg_ctx, 0);
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tcg_gen_add2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
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tcg_gen_sub2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
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gen_ext(s, QREG_CC_N, QREG_CC_N, opsize, 1);
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tcg_gen_andi_i32(tcg_ctx, QREG_CC_X, QREG_CC_X, 1);
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/* Compute signed-overflow for substract. */
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tcg_gen_xor_i32(tcg_ctx, QREG_CC_V, QREG_CC_N, dest);
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tcg_gen_xor_i32(tcg_ctx, tmp, dest, src);
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tcg_gen_and_i32(tcg_ctx, QREG_CC_V, QREG_CC_V, tmp);
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tcg_temp_free(tcg_ctx, tmp);
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/* Copy the rest of the results into place. */
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tcg_gen_or_i32(tcg_ctx, QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_C, QREG_CC_X);
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set_cc_op(s, CC_OP_FLAGS);
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/* result is in QREG_CC_N */
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}
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DISAS_INSN(subx_reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv dest;
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TCGv src;
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int opsize;
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opsize = insn_opsize(insn);
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src = gen_extend(s, DREG(insn, 0), opsize, 1);
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dest = gen_extend(s, DREG(insn, 9), opsize, 1);
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gen_subx(s, src, dest, opsize);
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gen_partset_reg(s, opsize, DREG(insn, 9), tcg_ctx->QREG_CC_N);
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}
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DISAS_INSN(subx_mem)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv src;
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TCGv addr_src;
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TCGv dest;
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TCGv addr_dest;
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int opsize;
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opsize = insn_opsize(insn);
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addr_src = AREG(insn, 0);
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tcg_gen_subi_i32(tcg_ctx, addr_src, addr_src, opsize);
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src = gen_load(s, opsize, addr_src, 1);
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addr_dest = AREG(insn, 9);
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tcg_gen_subi_i32(tcg_ctx, addr_dest, addr_dest, opsize);
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dest = gen_load(s, opsize, addr_dest, 1);
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gen_subx(s, src, dest, opsize);
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gen_store(s, opsize, addr_dest, tcg_ctx->QREG_CC_N);
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}
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DISAS_INSN(mov3q)
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@ -2155,16 +2261,82 @@ DISAS_INSN(adda)
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tcg_gen_add_i32(tcg_ctx, reg, reg, src);
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}
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DISAS_INSN(addx)
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static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv reg;
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TCGv src;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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TCGv tmp;
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gen_flush_flags(s);
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reg = DREG(insn, 9);
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src = DREG(insn, 0);
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gen_helper_addx_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, src);
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gen_flush_flags(s); /* compute old Z */
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/* Perform addition with carry.
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* (X, N) = src + dest + X;
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*/
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tmp = tcg_const_i32(tcg_ctx, 0);
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tcg_gen_add2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
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tcg_gen_add2_i32(tcg_ctx, QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
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gen_ext(s, QREG_CC_N, QREG_CC_N, opsize, 1);
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/* Compute signed-overflow for addition. */
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tcg_gen_xor_i32(tcg_ctx, QREG_CC_V, QREG_CC_N, src);
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tcg_gen_xor_i32(tcg_ctx, tmp, dest, src);
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tcg_gen_andc_i32(tcg_ctx, QREG_CC_V, QREG_CC_V, tmp);
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tcg_temp_free(tcg_ctx, tmp);
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/* Copy the rest of the results into place. */
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tcg_gen_or_i32(tcg_ctx, QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_C, QREG_CC_X);
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set_cc_op(s, CC_OP_FLAGS);
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/* result is in QREG_CC_N */
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}
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DISAS_INSN(addx_reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv dest;
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TCGv src;
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int opsize;
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opsize = insn_opsize(insn);
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dest = gen_extend(s, DREG(insn, 9), opsize, 1);
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src = gen_extend(s, DREG(insn, 0), opsize, 1);
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gen_addx(s, src, dest, opsize);
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gen_partset_reg(s, opsize, DREG(insn, 9), tcg_ctx->QREG_CC_N);
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}
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DISAS_INSN(addx_mem)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv src;
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TCGv addr_src;
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TCGv dest;
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TCGv addr_dest;
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int opsize;
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opsize = insn_opsize(insn);
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addr_src = AREG(insn, 0);
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tcg_gen_subi_i32(tcg_ctx, addr_src, addr_src, opsize_bytes(opsize));
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src = gen_load(s, opsize, addr_src, 1);
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addr_dest = AREG(insn, 9);
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tcg_gen_subi_i32(tcg_ctx, addr_dest, addr_dest, opsize_bytes(opsize));
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dest = gen_load(s, opsize, addr_dest, 1);
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gen_addx(s, src, dest, opsize);
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gen_store(s, opsize, addr_dest, tcg_ctx->QREG_CC_N);
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}
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/* TODO: This could be implemented without helper functions. */
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@ -3192,6 +3364,8 @@ void register_m68k_insns (CPUM68KState *env)
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BASE(move, 3000, f000);
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INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
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INSN(negx, 4080, fff8, CF_ISA_A);
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INSN(negx, 4000, ff00, M68000);
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INSN(undef, 40c0, ffc0, M68000);
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INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
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INSN(move_from_sr, 40c0, ffc0, M68000);
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BASE(lea, 41c0, f1c0);
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@ -3262,7 +3436,10 @@ void register_m68k_insns (CPUM68KState *env)
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BASE(or, 8000, f000);
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BASE(divw, 80c0, f0c0);
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BASE(addsub, 9000, f000);
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INSN(subx, 9180, f1f8, CF_ISA_A);
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INSN(undef, 90c0, f0c0, CF_ISA_A);
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INSN(subx_reg, 9180, f1f8, CF_ISA_A);
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INSN(subx_reg, 9100, f138, M68000);
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INSN(subx_mem, 9108, f138, M68000);
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INSN(suba, 91c0, f1c0, CF_ISA_A);
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BASE(undef_mac, a000, f000);
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@ -3294,7 +3471,10 @@ void register_m68k_insns (CPUM68KState *env)
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INSN(exg_da, c188, f1f8, M68000);
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BASE(mulw, c0c0, f0c0);
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BASE(addsub, d000, f000);
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INSN(addx, d180, f1f8, CF_ISA_A);
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INSN(undef, d0c0, f0c0, CF_ISA_A);
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INSN(addx_reg, d180, f1f8, CF_ISA_A);
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INSN(addx_reg, d100, f138, M68000);
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INSN(addx_mem, d108, f138, M68000);
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INSN(adda, d1c0, f1c0, CF_ISA_A);
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INSN(adda, d0c0, f0c0, M68000);
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INSN(shift_im, e080, f0f0, CF_ISA_A);
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