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tcg/s390: Handle clz opcode

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Backports commit ce411066f4886cf3a4981fc0a070042a221a5fc8 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 16:24:27 -05:00 committed by Lioncash
parent a90e026c18
commit 54ca83b900
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 36 additions and 2 deletions
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2
qemu/tcg/s390/tcg-target.h
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@ -110,7 +110,7 @@ extern uint64_t s390_facilities;
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM)
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)

36
qemu/tcg/s390/tcg-target.inc.c
View file

@ -50,7 +50,7 @@
#define TCG_REG_NONE 0
/* A scratch register that may be be used throughout the backend. */
#define TCG_TMP0 TCG_REG_R14
#define TCG_TMP0 TCG_REG_R1
#ifdef CONFIG_USE_GUEST_BASE
#define TCG_GUEST_BASE_REG TCG_REG_R13
@ -138,6 +138,7 @@ typedef enum S390Opcode {
RRE_DLR = 0xb997,
RRE_DSGFR = 0xb91d,
RRE_DSGR = 0xb90d,
RRE_FLOGR = 0xb983,
RRE_LGBR = 0xb906,
RRE_LCGR = 0xb903,
RRE_LGFR = 0xb914,
@ -1252,6 +1253,33 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
}
}
static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
TCGArg a2, int a2const)
{
/* Since this sets both R and R+1, we have no choice but to store the
result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
if (a2const && a2 == 64) {
tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
} else {
if (a2const) {
tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
} else {
tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
}
if (s390_facilities & FACILITY_LOAD_ON_COND) {
/* Emit: if (one bit found) dest = r0. */
tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
} else {
/* Emit: if (no one bit found) goto over; dest = r0; over: */
tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
}
}
}
static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
int ofs, int len, int z)
{
@ -2193,6 +2221,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tgen_extract(s, args[0], args[1], args[2], args[3]);
break;
case INDEX_op_clz_i64:
tgen_clz(s, args[0], args[1], args[2], const_args[2]);
break;
case INDEX_op_mb:
/* The host memory model is quite strong, we simply need to
serialize the instruction stream. */
@ -2254,6 +2286,8 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_bswap16_i32, { "r", "r" } },
{ INDEX_op_bswap32_i32, { "r", "r" } },
{ INDEX_op_clz_i64, { "r", "r", "ri" } },
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } },