mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-11 05:46:12 +00:00
target/arm: Perform fpdp_v2 check first
Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
7e99995b7b
commit
54e9ce5174
|
|
@ -204,12 +204,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
|
|||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vn | a->vd) & 0x10)) {
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vn | a->vd) & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -337,13 +338,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vn | a->vd) & 0x10)) {
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vn | a->vd) & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -424,13 +425,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vd) & 0x10)) {
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vm | a->vd) & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -489,12 +490,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -1329,12 +1330,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
|
|||
TCGv_i64 f0, f1, fd;
|
||||
TCGv_ptr fpst;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -1480,6 +1481,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
|
|||
int veclen = s->vec_len;
|
||||
TCGv_i64 f0, fd;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
|
||||
return false;
|
||||
|
|
@ -1490,10 +1495,6 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -1851,7 +1852,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) &&
|
||||
((a->vd | a->vn | a->vm) & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -1947,12 +1950,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
|
|||
|
||||
vd = a->vd;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -2088,6 +2091,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
|
|||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
TCGv_i64 vd, vm;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Vm/M bits must be zero for the Z variant */
|
||||
if (a->z && a->vm != 0) {
|
||||
return false;
|
||||
|
|
@ -2098,10 +2105,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2164,6 +2167,11 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
|
|||
TCGv_i32 tmp;
|
||||
TCGv_i64 vd;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2173,10 +2181,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2232,6 +2236,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
|
|||
TCGv_i32 tmp;
|
||||
TCGv_i64 vm;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2241,10 +2249,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2294,6 +2298,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
|
|||
TCGv_ptr fpst;
|
||||
TCGv_i64 tmp;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_vrint, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2303,10 +2311,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2357,6 +2361,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
|
|||
TCGv_i64 tmp;
|
||||
TCGv_i32 tcg_rmode;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_vrint, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2366,10 +2374,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2418,6 +2422,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
|
|||
TCGv_ptr fpst;
|
||||
TCGv_i64 tmp;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_vrint, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2427,10 +2435,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2451,12 +2455,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
|
|||
TCGv_i64 vd;
|
||||
TCGv_i32 vm;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -2480,12 +2484,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
|
|||
TCGv_i64 vm;
|
||||
TCGv_i32 vd;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -2536,12 +2540,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
|
|||
TCGv_i64 vd;
|
||||
TCGv_ptr fpst;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -2573,6 +2577,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
|
|||
TCGv_i32 vd;
|
||||
TCGv_i64 vm;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_jscvt, s)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2582,10 +2590,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2668,6 +2672,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
|
|||
TCGv_ptr fpst;
|
||||
int frac_bits;
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -2677,10 +2685,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
|
|||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
|
@ -2770,12 +2774,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
|
|||
TCGv_i64 vm;
|
||||
TCGv_ptr fpst;
|
||||
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
|
||||
/* UNDEF accesses to D16-D31 if they don't exist. */
|
||||
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue