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https://github.com/yuzu-emu/unicorn.git
synced 2025-03-23 06:25:12 +00:00
target-m68k: Delay autoinc writeback
Backports commit 8a1e52b69d2cd1c633f3c473a213d575931bf46d from qemu
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c7ab1e782b
commit
5541553e8d
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@ -37,12 +37,12 @@
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#define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
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#define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
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#define REG(insn, pos) (((insn) >> (pos)) & 7)
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#define REG(insn, pos) (((insn) >> (pos)) & 7)
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#define DREG(insn, pos) tcg_ctx->cpu_dregs[REG(insn, pos)]
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#define AREG(insn, pos) tcg_ctx->cpu_aregs[REG(insn, pos)]
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#define AREG(insn, pos) get_areg(s, REG(insn, pos))
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#define FREG(insn, pos) tcg_ctx->cpu_fregs[REG(insn, pos)]
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#define MACREG(acc) tcg_ctx->cpu_macc[acc]
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#define QREG_SP tcg_ctx->cpu_aregs[7]
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#define MACREG(acc) tcg_ctx->cpu_macc[acc]
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#define QREG_SP tcg_ctx->cpu_aregs[7]
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#define IS_NULL_QREG(t) (TCGV_EQUAL(t, tcg_ctx->NULL_QREG))
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@ -113,11 +113,64 @@ typedef struct DisasContext {
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int singlestep_enabled;
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TCGv_i64 mactmp;
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int done_mac;
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int writeback_mask;
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TCGv writeback[8];
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// Unicorn engine
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struct uc_struct *uc;
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} DisasContext;
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static TCGv get_areg(DisasContext *s, unsigned regno)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (s->writeback_mask & (1 << regno)) {
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return s->writeback[regno];
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} else {
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return tcg_ctx->cpu_aregs[regno];
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}
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}
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static void delay_set_areg(DisasContext *s, unsigned regno,
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TCGv val, bool give_temp)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (s->writeback_mask & (1 << regno)) {
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if (give_temp) {
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tcg_temp_free(tcg_ctx, s->writeback[regno]);
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s->writeback[regno] = val;
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} else {
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tcg_gen_mov_i32(tcg_ctx, s->writeback[regno], val);
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}
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} else {
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s->writeback_mask |= 1 << regno;
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if (give_temp) {
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s->writeback[regno] = val;
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} else {
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TCGv tmp = tcg_temp_new(tcg_ctx);
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s->writeback[regno] = tmp;
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tcg_gen_mov_i32(tcg_ctx, tmp, val);
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}
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}
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}
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static void do_writebacks(DisasContext *s)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned mask = s->writeback_mask;
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if (mask) {
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s->writeback_mask = 0;
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do {
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unsigned regno = ctz32(mask);
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_aregs[regno], s->writeback[regno]);
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tcg_temp_free(tcg_ctx, s->writeback[regno]);
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mask &= mask - 1;
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} while (mask);
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}
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}
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#define DISAS_JUMP_NEXT 4
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#if defined(CONFIG_USER_ONLY)
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@ -751,10 +804,11 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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case 3: /* Indirect postincrement. */
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reg = AREG(insn, 0);
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result = gen_ldst(s, opsize, reg, val, what);
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/* ??? This is not exception safe. The instruction may still
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fault after this point. */
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if (what == EA_STORE || !addrp)
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tcg_gen_addi_i32(tcg_ctx, reg, reg, opsize_bytes(opsize));
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if (what == EA_STORE || !addrp) {
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TCGv tmp = tcg_temp_new(tcg_ctx);
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tcg_gen_addi_i32(tcg_ctx, tmp, reg, opsize_bytes(opsize));
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delay_set_areg(s, REG(insn, 0), tmp, true);
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}
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return result;
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case 4: /* Indirect predecrememnt. */
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{
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@ -769,11 +823,8 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
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*addrp = tmp;
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}
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result = gen_ldst(s, opsize, tmp, val, what);
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/* ??? This is not exception safe. The instruction may still
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fault after this point. */
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if (what == EA_STORE || !addrp) {
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reg = AREG(insn, 0);
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tcg_gen_mov_i32(tcg_ctx, reg, tmp);
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delay_set_areg(s, REG(insn, 0), tmp, false);
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}
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}
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return result;
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@ -3558,7 +3609,6 @@ void register_m68k_insns (CPUM68KState *env)
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static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint16_t insn;
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// Unicorn: end address tells us to stop emulation
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if (s->pc == s->uc->addr_end) {
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@ -3573,9 +3623,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
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check_exit_request(tcg_ctx);
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}
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insn = read_im16(env, s);
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uint16_t insn = read_im16(env, s);
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((disas_proc)tcg_ctx->opcode_table[insn])(env, s, insn);
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do_writebacks(s);
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}
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/* generate intermediate code for basic block 'tb'. */
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@ -3606,6 +3656,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
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dc->fpcr = env->fpcr;
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dc->user = (env->sr & SR_S) == 0;
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dc->done_mac = 0;
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dc->writeback_mask = 0;
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num_insns = 0;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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