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target/arm: Emit barriers for A32/T32 load-acquire/store-release insns

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Now that MTTCG is here, the comment in the 32-bit Arm decoder that
"Since the emulation does not have barriers, the acquire/release
semantics need no special handling" is no longer true. Emit the
correct barriers for the load-acquire/store-release insns, as
we already do in the A64 decoder.

Backports commit 96c552958dbb63453b5f02bea6e704006d50e39a from qemu
This commit is contained in:
Peter Maydell 2019-01-13 19:48:18 -05:00 committed by Lioncash
parent 254f882efc
commit 55bc017af4
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 26 additions and 7 deletions
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33
qemu/target/arm/translate.c
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@ -9921,6 +9921,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
rd = (insn >> 12) & 0xf;
if (insn & (1 << 23)) {
/* load/store exclusive */
bool is_ld = extract32(insn, 20, 1);
bool is_lasr = !extract32(insn, 8, 1);
int op2 = (insn >> 8) & 3;
op1 = (insn >> 21) & 0x3;
@ -9948,11 +9950,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
addr = tcg_temp_local_new_i32(tcg_ctx);
load_reg_var(s, addr, rn);
/* Since the emulation does not have barriers,
the acquire/release semantics need no special
handling */
if (is_lasr && !is_ld) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL);
}
if (op2 == 0) {
if (insn & (1 << 20)) {
if (is_ld) {
tmp = tcg_temp_new_i32(tcg_ctx);
switch (op1) {
case 0: /* lda */
@ -9998,7 +10001,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
tcg_temp_free_i32(tcg_ctx, tmp);
}
} else if (insn & (1 << 20)) {
} else if (is_ld) {
switch (op1) {
case 0: /* ldrex */
gen_load_exclusive(s, rd, 15, addr, 2);
@ -10035,6 +10038,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
}
tcg_temp_free_i32(tcg_ctx, addr);
if (is_lasr && is_ld) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
}
} else if ((insn & 0x00300f00) == 0) {
/* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
* - SWP, SWPB
@ -11046,6 +11053,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_gen_addi_i32(tcg_ctx, tmp, tmp, s->pc);
store_reg(s, 15, tmp);
} else {
bool is_lasr = false;
bool is_ld = extract32(insn, 20, 1);
int op2 = (insn >> 6) & 0x3;
op = (insn >> 4) & 0x3;
switch (op2) {
@ -11067,12 +11076,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 3:
/* Load-acquire/store-release exclusive */
ARCH(8);
is_lasr = true;
break;
}
if (is_lasr && !is_ld) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL);
}
addr = tcg_temp_local_new_i32(tcg_ctx);
load_reg_var(s, addr, rn);
if (!(op2 & 1)) {
if (insn & (1 << 20)) {
if (is_ld) {
tmp = tcg_temp_new_i32(tcg_ctx);
switch (op) {
case 0: /* ldab */
@ -11111,12 +11126,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
tcg_temp_free_i32(tcg_ctx, tmp);
}
} else if (insn & (1 << 20)) {
} else if (is_ld) {
gen_load_exclusive(s, rs, rd, addr, op);
} else {
gen_store_exclusive(s, rm, rs, rd, addr, op);
}
tcg_temp_free_i32(tcg_ctx, addr);
if (is_lasr && is_ld) {
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
}
}
} else {
/* Load/store multiple, RFE, SRS. */