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riscv: Fix bug in setting pmpcfg CSR for RISCV64

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First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.

If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.

We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).

Backports fdd33b86b20d153b131fc6259aea7a0084ab14b8
This commit is contained in:
Hou Weiying 2021-03-08 12:42:01 -05:00 committed by Lioncash
parent cde007ccb6
commit 55be7adad9
1 changed files with 2 additions and 3 deletions
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5
qemu/target/riscv/pmp.c
View file

@ -316,8 +316,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
for (i = 0; i < sizeof(target_ulong); i++) {
cfg_val = (val >> 8 * i) & 0xff;
pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
cfg_val);
pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
}
@ -332,7 +331,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
target_ulong val = 0;
for (i = 0; i < sizeof(target_ulong); i++) {
val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
val = pmp_read_cfg(env, (reg_index * 4) + i);
cfg_val |= (val << (i * 8));
}