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target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*
They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Backports commit 19cbd87c14ab208858ee1233b790f37cfefed4b9 from qemu
This commit is contained in:
Eduardo Habkost
Lioncash
parent
e90dbe6bb9
commit
566acb7188
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@ -750,24 +750,24 @@ typedef struct BNDCSReg {
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} BNDCSReg;
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#ifdef HOST_WORDS_BIGENDIAN
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#define XMM_B(n) _b[63 - (n)]
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#define XMM_W(n) _w[31 - (n)]
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#define XMM_L(n) _l[15 - (n)]
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#define XMM_S(n) _s[15 - (n)]
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#define XMM_Q(n) _q[7 - (n)]
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#define XMM_D(n) _d[7 - (n)]
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#define ZMM_B(n) _b[63 - (n)]
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#define ZMM_W(n) _w[31 - (n)]
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#define ZMM_L(n) _l[15 - (n)]
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#define ZMM_S(n) _s[15 - (n)]
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#define ZMM_Q(n) _q[7 - (n)]
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#define ZMM_D(n) _d[7 - (n)]
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#define MMX_B(n) _b[7 - (n)]
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#define MMX_W(n) _w[3 - (n)]
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#define MMX_L(n) _l[1 - (n)]
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#define MMX_S(n) _s[1 - (n)]
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#else
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#define XMM_B(n) _b[n]
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#define XMM_W(n) _w[n]
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#define XMM_L(n) _l[n]
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#define XMM_S(n) _s[n]
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#define XMM_Q(n) _q[n]
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#define XMM_D(n) _d[n]
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#define ZMM_B(n) _b[n]
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#define ZMM_W(n) _w[n]
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#define ZMM_L(n) _l[n]
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#define ZMM_S(n) _s[n]
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#define ZMM_Q(n) _q[n]
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#define ZMM_D(n) _d[n]
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#define MMX_B(n) _b[n]
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#define MMX_W(n) _w[n]
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@ -1199,8 +1199,8 @@ static void do_fxsave(CPUX86State *env, target_ulong ptr, int data64,
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|| (env->hflags & HF_CPL_MASK)
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|| !(env->hflags & HF_LMA_MASK)) {
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for (i = 0; i < nb_xmm_regs; i++) {
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cpu_stq_data_ra(env, addr, env->xmm_regs[i].XMM_Q(0), retaddr);
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cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].XMM_Q(1), retaddr);
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cpu_stq_data_ra(env, addr, env->xmm_regs[i].ZMM_Q(0), retaddr);
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cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].ZMM_Q(1), retaddr);
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addr += 16;
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}
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}
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@ -1256,8 +1256,8 @@ static void do_fxrstor(CPUX86State *env, target_ulong ptr, int data64,
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|| (env->hflags & HF_CPL_MASK)
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|| !(env->hflags & HF_LMA_MASK)) {
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for (i = 0; i < nb_xmm_regs; i++) {
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env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data_ra(env, addr, retaddr);
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env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data_ra(env, addr + 8, retaddr);
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env->xmm_regs[i].ZMM_Q(0) = cpu_ldq_data_ra(env, addr, retaddr);
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env->xmm_regs[i].ZMM_Q(1) = cpu_ldq_data_ra(env, addr + 8, retaddr);
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addr += 16;
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}
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}
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@ -343,10 +343,10 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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for(i=0;i<nb;i++) {
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cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
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i,
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env->xmm_regs[i].XMM_L(3),
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env->xmm_regs[i].XMM_L(2),
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env->xmm_regs[i].XMM_L(1),
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env->xmm_regs[i].XMM_L(0));
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env->xmm_regs[i].ZMM_L(3),
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env->xmm_regs[i].ZMM_L(2),
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env->xmm_regs[i].ZMM_L(1),
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env->xmm_regs[i].ZMM_L(0));
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if ((i & 1) == 1)
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cpu_fprintf(f, "\n");
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else
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@ -22,7 +22,7 @@
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#if SHIFT == 0
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#define Reg MMXReg
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#define XMM_ONLY(...)
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#define ZMM_ONLY(...)
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#define B(n) MMX_B(n)
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#define W(n) MMX_W(n)
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#define L(n) MMX_L(n)
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@ -30,11 +30,11 @@
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#define SUFFIX _mmx
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#else
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#define Reg ZMMReg
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#define XMM_ONLY(...) __VA_ARGS__
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#define B(n) XMM_B(n)
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#define W(n) XMM_W(n)
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#define L(n) XMM_L(n)
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#define Q(n) XMM_Q(n)
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#define ZMM_ONLY(...) __VA_ARGS__
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#define B(n) ZMM_B(n)
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#define W(n) ZMM_W(n)
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#define L(n) ZMM_L(n)
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#define Q(n) ZMM_Q(n)
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#define SUFFIX _xmm
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#endif
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@ -245,7 +245,7 @@ void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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d->B(5) = F(d->B(5), s->B(5)); \
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d->B(6) = F(d->B(6), s->B(6)); \
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d->B(7) = F(d->B(7), s->B(7)); \
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XMM_ONLY( \
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ZMM_ONLY( \
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d->B(8) = F(d->B(8), s->B(8)); \
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d->B(9) = F(d->B(9), s->B(9)); \
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d->B(10) = F(d->B(10), s->B(10)); \
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@ -264,7 +264,7 @@ void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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d->W(1) = F(d->W(1), s->W(1)); \
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d->W(2) = F(d->W(2), s->W(2)); \
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d->W(3) = F(d->W(3), s->W(3)); \
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XMM_ONLY( \
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ZMM_ONLY( \
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d->W(4) = F(d->W(4), s->W(4)); \
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d->W(5) = F(d->W(5), s->W(5)); \
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d->W(6) = F(d->W(6), s->W(6)); \
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@ -277,7 +277,7 @@ void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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{ \
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d->L(0) = F(d->L(0), s->L(0)); \
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d->L(1) = F(d->L(1), s->L(1)); \
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XMM_ONLY( \
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ZMM_ONLY( \
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d->L(2) = F(d->L(2), s->L(2)); \
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d->L(3) = F(d->L(3), s->L(3)); \
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) \
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@ -287,7 +287,7 @@ void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
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{ \
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d->Q(0) = F(d->Q(0), s->Q(0)); \
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XMM_ONLY( \
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ZMM_ONLY( \
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d->Q(1) = F(d->Q(1), s->Q(1)); \
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) \
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}
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@ -582,26 +582,26 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
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#define SSE_HELPER_S(name, F) \
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void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
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{ \
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d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
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d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \
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d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \
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d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \
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d->ZMM_S(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
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d->ZMM_S(1) = F(32, d->ZMM_S(1), s->ZMM_S(1)); \
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d->ZMM_S(2) = F(32, d->ZMM_S(2), s->ZMM_S(2)); \
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d->ZMM_S(3) = F(32, d->ZMM_S(3), s->ZMM_S(3)); \
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} \
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\
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void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
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{ \
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d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
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d->ZMM_S(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
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} \
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\
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void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
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{ \
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d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
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d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \
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d->ZMM_D(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
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d->ZMM_D(1) = F(64, d->ZMM_D(1), s->ZMM_D(1)); \
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} \
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\
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void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
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{ \
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d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
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d->ZMM_D(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
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}
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#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
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@ -633,216 +633,216 @@ void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s)
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{
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float32 s0, s1;
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s0 = s->XMM_S(0);
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s1 = s->XMM_S(1);
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d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
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d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
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s0 = s->ZMM_S(0);
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s1 = s->ZMM_S(1);
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d->ZMM_D(0) = float32_to_float64(s0, &env->sse_status);
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d->ZMM_D(1) = float32_to_float64(s1, &env->sse_status);
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}
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void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s)
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{
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d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
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d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status);
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d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
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d->ZMM_S(1) = float64_to_float32(s->ZMM_D(1), &env->sse_status);
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d->Q(1) = 0;
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}
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void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
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{
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d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status);
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d->ZMM_D(0) = float32_to_float64(s->ZMM_S(0), &env->sse_status);
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}
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void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
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{
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d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
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d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
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}
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/* integer to float */
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void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s)
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{
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d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status);
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d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status);
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d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status);
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d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status);
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d->ZMM_S(0) = int32_to_float32(s->ZMM_L(0), &env->sse_status);
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d->ZMM_S(1) = int32_to_float32(s->ZMM_L(1), &env->sse_status);
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d->ZMM_S(2) = int32_to_float32(s->ZMM_L(2), &env->sse_status);
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d->ZMM_S(3) = int32_to_float32(s->ZMM_L(3), &env->sse_status);
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}
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void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s)
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{
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int32_t l0, l1;
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l0 = (int32_t)s->XMM_L(0);
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l1 = (int32_t)s->XMM_L(1);
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d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
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d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
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l0 = (int32_t)s->ZMM_L(0);
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l1 = (int32_t)s->ZMM_L(1);
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d->ZMM_D(0) = int32_to_float64(l0, &env->sse_status);
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d->ZMM_D(1) = int32_to_float64(l1, &env->sse_status);
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}
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void helper_cvtpi2ps(CPUX86State *env, ZMMReg *d, MMXReg *s)
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{
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d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
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d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
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d->ZMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
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d->ZMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
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}
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void helper_cvtpi2pd(CPUX86State *env, ZMMReg *d, MMXReg *s)
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{
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d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
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d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
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d->ZMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
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d->ZMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
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}
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void helper_cvtsi2ss(CPUX86State *env, ZMMReg *d, uint32_t val)
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{
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d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
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d->ZMM_S(0) = int32_to_float32(val, &env->sse_status);
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}
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void helper_cvtsi2sd(CPUX86State *env, ZMMReg *d, uint32_t val)
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{
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d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
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d->ZMM_D(0) = int32_to_float64(val, &env->sse_status);
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}
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#ifdef TARGET_X86_64
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void helper_cvtsq2ss(CPUX86State *env, ZMMReg *d, uint64_t val)
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{
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d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
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d->ZMM_S(0) = int64_to_float32(val, &env->sse_status);
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}
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void helper_cvtsq2sd(CPUX86State *env, ZMMReg *d, uint64_t val)
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{
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d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
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d->ZMM_D(0) = int64_to_float64(val, &env->sse_status);
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}
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#endif
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/* float to integer */
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void helper_cvtps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
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{
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d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
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d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
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d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status);
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d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
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d->ZMM_L(0) = float32_to_int32(s->ZMM_S(0), &env->sse_status);
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d->ZMM_L(1) = float32_to_int32(s->ZMM_S(1), &env->sse_status);
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d->ZMM_L(2) = float32_to_int32(s->ZMM_S(2), &env->sse_status);
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d->ZMM_L(3) = float32_to_int32(s->ZMM_S(3), &env->sse_status);
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}
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void helper_cvtpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
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{
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d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
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d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
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d->XMM_Q(1) = 0;
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d->ZMM_L(0) = float64_to_int32(s->ZMM_D(0), &env->sse_status);
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d->ZMM_L(1) = float64_to_int32(s->ZMM_D(1), &env->sse_status);
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d->ZMM_Q(1) = 0;
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}
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void helper_cvtps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
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{
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d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
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d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
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d->MMX_L(0) = float32_to_int32(s->ZMM_S(0), &env->sse_status);
|
||||
d->MMX_L(1) = float32_to_int32(s->ZMM_S(1), &env->sse_status);
|
||||
}
|
||||
|
||||
void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
|
||||
{
|
||||
d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
|
||||
d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
|
||||
d->MMX_L(0) = float64_to_int32(s->ZMM_D(0), &env->sse_status);
|
||||
d->MMX_L(1) = float64_to_int32(s->ZMM_D(1), &env->sse_status);
|
||||
}
|
||||
|
||||
int32_t helper_cvtss2si(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float32_to_int32(s->XMM_S(0), &env->sse_status);
|
||||
return float32_to_int32(s->ZMM_S(0), &env->sse_status);
|
||||
}
|
||||
|
||||
int32_t helper_cvtsd2si(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float64_to_int32(s->XMM_D(0), &env->sse_status);
|
||||
return float64_to_int32(s->ZMM_D(0), &env->sse_status);
|
||||
}
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
int64_t helper_cvtss2sq(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float32_to_int64(s->XMM_S(0), &env->sse_status);
|
||||
return float32_to_int64(s->ZMM_S(0), &env->sse_status);
|
||||
}
|
||||
|
||||
int64_t helper_cvtsd2sq(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float64_to_int64(s->XMM_D(0), &env->sse_status);
|
||||
return float64_to_int64(s->ZMM_D(0), &env->sse_status);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* float to integer truncated */
|
||||
void helper_cvttps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
|
||||
d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
|
||||
d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status);
|
||||
d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
|
||||
d->ZMM_L(0) = float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
|
||||
d->ZMM_L(1) = float32_to_int32_round_to_zero(s->ZMM_S(1), &env->sse_status);
|
||||
d->ZMM_L(2) = float32_to_int32_round_to_zero(s->ZMM_S(2), &env->sse_status);
|
||||
d->ZMM_L(3) = float32_to_int32_round_to_zero(s->ZMM_S(3), &env->sse_status);
|
||||
}
|
||||
|
||||
void helper_cvttpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
|
||||
d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
|
||||
d->XMM_Q(1) = 0;
|
||||
d->ZMM_L(0) = float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
|
||||
d->ZMM_L(1) = float64_to_int32_round_to_zero(s->ZMM_D(1), &env->sse_status);
|
||||
d->ZMM_Q(1) = 0;
|
||||
}
|
||||
|
||||
void helper_cvttps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
|
||||
{
|
||||
d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
|
||||
d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
|
||||
d->MMX_L(0) = float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
|
||||
d->MMX_L(1) = float32_to_int32_round_to_zero(s->ZMM_S(1), &env->sse_status);
|
||||
}
|
||||
|
||||
void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
|
||||
{
|
||||
d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
|
||||
d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
|
||||
d->MMX_L(0) = float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
|
||||
d->MMX_L(1) = float64_to_int32_round_to_zero(s->ZMM_D(1), &env->sse_status);
|
||||
}
|
||||
|
||||
int32_t helper_cvttss2si(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
|
||||
return float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
|
||||
}
|
||||
|
||||
int32_t helper_cvttsd2si(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
|
||||
return float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
|
||||
}
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
int64_t helper_cvttss2sq(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
|
||||
return float32_to_int64_round_to_zero(s->ZMM_S(0), &env->sse_status);
|
||||
}
|
||||
|
||||
int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s)
|
||||
{
|
||||
return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
|
||||
return float64_to_int64_round_to_zero(s->ZMM_D(0), &env->sse_status);
|
||||
}
|
||||
#endif
|
||||
|
||||
void helper_rsqrtps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_S(0) = float32_div(float32_one,
|
||||
float32_sqrt(s->XMM_S(0), &env->sse_status),
|
||||
d->ZMM_S(0) = float32_div(float32_one,
|
||||
float32_sqrt(s->ZMM_S(0), &env->sse_status),
|
||||
&env->sse_status);
|
||||
d->XMM_S(1) = float32_div(float32_one,
|
||||
float32_sqrt(s->XMM_S(1), &env->sse_status),
|
||||
d->ZMM_S(1) = float32_div(float32_one,
|
||||
float32_sqrt(s->ZMM_S(1), &env->sse_status),
|
||||
&env->sse_status);
|
||||
d->XMM_S(2) = float32_div(float32_one,
|
||||
float32_sqrt(s->XMM_S(2), &env->sse_status),
|
||||
d->ZMM_S(2) = float32_div(float32_one,
|
||||
float32_sqrt(s->ZMM_S(2), &env->sse_status),
|
||||
&env->sse_status);
|
||||
d->XMM_S(3) = float32_div(float32_one,
|
||||
float32_sqrt(s->XMM_S(3), &env->sse_status),
|
||||
d->ZMM_S(3) = float32_div(float32_one,
|
||||
float32_sqrt(s->ZMM_S(3), &env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
|
||||
void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_S(0) = float32_div(float32_one,
|
||||
float32_sqrt(s->XMM_S(0), &env->sse_status),
|
||||
d->ZMM_S(0) = float32_div(float32_one,
|
||||
float32_sqrt(s->ZMM_S(0), &env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
|
||||
void helper_rcpps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
|
||||
d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status);
|
||||
d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status);
|
||||
d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status);
|
||||
d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
|
||||
d->ZMM_S(1) = float32_div(float32_one, s->ZMM_S(1), &env->sse_status);
|
||||
d->ZMM_S(2) = float32_div(float32_one, s->ZMM_S(2), &env->sse_status);
|
||||
d->ZMM_S(3) = float32_div(float32_one, s->ZMM_S(3), &env->sse_status);
|
||||
}
|
||||
|
||||
void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
|
||||
d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
|
||||
}
|
||||
|
||||
static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
|
||||
|
|
@ -859,12 +859,12 @@ static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
|
|||
|
||||
void helper_extrq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0));
|
||||
d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), s->ZMM_B(1), s->ZMM_B(0));
|
||||
}
|
||||
|
||||
void helper_extrq_i(CPUX86State *env, ZMMReg *d, int index, int length)
|
||||
{
|
||||
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length);
|
||||
d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), index, length);
|
||||
}
|
||||
|
||||
static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
|
||||
|
|
@ -881,22 +881,22 @@ static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
|
|||
|
||||
void helper_insertq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8));
|
||||
d->ZMM_Q(0) = helper_insertq(s->ZMM_Q(0), s->ZMM_B(9), s->ZMM_B(8));
|
||||
}
|
||||
|
||||
void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length)
|
||||
{
|
||||
d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length);
|
||||
d->ZMM_Q(0) = helper_insertq(d->ZMM_Q(0), index, length);
|
||||
}
|
||||
|
||||
void helper_haddps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
ZMMReg r;
|
||||
|
||||
r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
|
||||
r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
|
||||
r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
|
||||
r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
|
||||
r.ZMM_S(0) = float32_add(d->ZMM_S(0), d->ZMM_S(1), &env->sse_status);
|
||||
r.ZMM_S(1) = float32_add(d->ZMM_S(2), d->ZMM_S(3), &env->sse_status);
|
||||
r.ZMM_S(2) = float32_add(s->ZMM_S(0), s->ZMM_S(1), &env->sse_status);
|
||||
r.ZMM_S(3) = float32_add(s->ZMM_S(2), s->ZMM_S(3), &env->sse_status);
|
||||
*d = r;
|
||||
}
|
||||
|
||||
|
|
@ -904,8 +904,8 @@ void helper_haddpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
|||
{
|
||||
ZMMReg r;
|
||||
|
||||
r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
|
||||
r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
|
||||
r.ZMM_D(0) = float64_add(d->ZMM_D(0), d->ZMM_D(1), &env->sse_status);
|
||||
r.ZMM_D(1) = float64_add(s->ZMM_D(0), s->ZMM_D(1), &env->sse_status);
|
||||
*d = r;
|
||||
}
|
||||
|
||||
|
|
@ -913,10 +913,10 @@ void helper_hsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
|||
{
|
||||
ZMMReg r;
|
||||
|
||||
r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
|
||||
r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
|
||||
r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
|
||||
r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
|
||||
r.ZMM_S(0) = float32_sub(d->ZMM_S(0), d->ZMM_S(1), &env->sse_status);
|
||||
r.ZMM_S(1) = float32_sub(d->ZMM_S(2), d->ZMM_S(3), &env->sse_status);
|
||||
r.ZMM_S(2) = float32_sub(s->ZMM_S(0), s->ZMM_S(1), &env->sse_status);
|
||||
r.ZMM_S(3) = float32_sub(s->ZMM_S(2), s->ZMM_S(3), &env->sse_status);
|
||||
*d = r;
|
||||
}
|
||||
|
||||
|
|
@ -924,49 +924,49 @@ void helper_hsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
|||
{
|
||||
ZMMReg r;
|
||||
|
||||
r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
|
||||
r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
|
||||
r.ZMM_D(0) = float64_sub(d->ZMM_D(0), d->ZMM_D(1), &env->sse_status);
|
||||
r.ZMM_D(1) = float64_sub(s->ZMM_D(0), s->ZMM_D(1), &env->sse_status);
|
||||
*d = r;
|
||||
}
|
||||
|
||||
void helper_addsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status);
|
||||
d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status);
|
||||
d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status);
|
||||
d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status);
|
||||
d->ZMM_S(0) = float32_sub(d->ZMM_S(0), s->ZMM_S(0), &env->sse_status);
|
||||
d->ZMM_S(1) = float32_add(d->ZMM_S(1), s->ZMM_S(1), &env->sse_status);
|
||||
d->ZMM_S(2) = float32_sub(d->ZMM_S(2), s->ZMM_S(2), &env->sse_status);
|
||||
d->ZMM_S(3) = float32_add(d->ZMM_S(3), s->ZMM_S(3), &env->sse_status);
|
||||
}
|
||||
|
||||
void helper_addsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
|
||||
{
|
||||
d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status);
|
||||
d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status);
|
||||
d->ZMM_D(0) = float64_sub(d->ZMM_D(0), s->ZMM_D(0), &env->sse_status);
|
||||
d->ZMM_D(1) = float64_add(d->ZMM_D(1), s->ZMM_D(1), &env->sse_status);
|
||||
}
|
||||
|
||||
/* XXX: unordered */
|
||||
#define SSE_HELPER_CMP(name, F) \
|
||||
void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
|
||||
{ \
|
||||
d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
|
||||
d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \
|
||||
d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \
|
||||
d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \
|
||||
d->ZMM_L(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
|
||||
d->ZMM_L(1) = F(32, d->ZMM_S(1), s->ZMM_S(1)); \
|
||||
d->ZMM_L(2) = F(32, d->ZMM_S(2), s->ZMM_S(2)); \
|
||||
d->ZMM_L(3) = F(32, d->ZMM_S(3), s->ZMM_S(3)); \
|
||||
} \
|
||||
\
|
||||
void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
|
||||
{ \
|
||||
d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
|
||||
d->ZMM_L(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
|
||||
} \
|
||||
\
|
||||
void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
|
||||
{ \
|
||||
d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
|
||||
d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \
|
||||
d->ZMM_Q(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
|
||||
d->ZMM_Q(1) = F(64, d->ZMM_D(1), s->ZMM_D(1)); \
|
||||
} \
|
||||
\
|
||||
void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
|
||||
{ \
|
||||
d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
|
||||
d->ZMM_Q(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
|
||||
}
|
||||
|
||||
#define FPU_CMPEQ(size, a, b) \
|
||||
|
|
@ -1002,8 +1002,8 @@ void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s)
|
|||
int ret;
|
||||
float32 s0, s1;
|
||||
|
||||
s0 = d->XMM_S(0);
|
||||
s1 = s->XMM_S(0);
|
||||
s0 = d->ZMM_S(0);
|
||||
s1 = s->ZMM_S(0);
|
||||
ret = float32_compare_quiet(s0, s1, &env->sse_status);
|
||||
CC_SRC = comis_eflags[ret + 1];
|
||||
}
|
||||
|
|
@ -1013,8 +1013,8 @@ void helper_comiss(CPUX86State *env, Reg *d, Reg *s)
|
|||
int ret;
|
||||
float32 s0, s1;
|
||||
|
||||
s0 = d->XMM_S(0);
|
||||
s1 = s->XMM_S(0);
|
||||
s0 = d->ZMM_S(0);
|
||||
s1 = s->ZMM_S(0);
|
||||
ret = float32_compare(s0, s1, &env->sse_status);
|
||||
CC_SRC = comis_eflags[ret + 1];
|
||||
}
|
||||
|
|
@ -1024,8 +1024,8 @@ void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s)
|
|||
int ret;
|
||||
float64 d0, d1;
|
||||
|
||||
d0 = d->XMM_D(0);
|
||||
d1 = s->XMM_D(0);
|
||||
d0 = d->ZMM_D(0);
|
||||
d1 = s->ZMM_D(0);
|
||||
ret = float64_compare_quiet(d0, d1, &env->sse_status);
|
||||
CC_SRC = comis_eflags[ret + 1];
|
||||
}
|
||||
|
|
@ -1035,8 +1035,8 @@ void helper_comisd(CPUX86State *env, Reg *d, Reg *s)
|
|||
int ret;
|
||||
float64 d0, d1;
|
||||
|
||||
d0 = d->XMM_D(0);
|
||||
d1 = s->XMM_D(0);
|
||||
d0 = d->ZMM_D(0);
|
||||
d1 = s->ZMM_D(0);
|
||||
ret = float64_compare(d0, d1, &env->sse_status);
|
||||
CC_SRC = comis_eflags[ret + 1];
|
||||
}
|
||||
|
|
@ -1045,10 +1045,10 @@ uint32_t helper_movmskps(CPUX86State *env, Reg *s)
|
|||
{
|
||||
int b0, b1, b2, b3;
|
||||
|
||||
b0 = s->XMM_L(0) >> 31;
|
||||
b1 = s->XMM_L(1) >> 31;
|
||||
b2 = s->XMM_L(2) >> 31;
|
||||
b3 = s->XMM_L(3) >> 31;
|
||||
b0 = s->ZMM_L(0) >> 31;
|
||||
b1 = s->ZMM_L(1) >> 31;
|
||||
b2 = s->ZMM_L(2) >> 31;
|
||||
b3 = s->ZMM_L(3) >> 31;
|
||||
return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
|
||||
}
|
||||
|
||||
|
|
@ -1056,8 +1056,8 @@ uint32_t helper_movmskpd(CPUX86State *env, Reg *s)
|
|||
{
|
||||
int b0, b1;
|
||||
|
||||
b0 = s->XMM_L(1) >> 31;
|
||||
b1 = s->XMM_L(3) >> 31;
|
||||
b0 = s->ZMM_L(1) >> 31;
|
||||
b1 = s->ZMM_L(3) >> 31;
|
||||
return b0 | (b1 << 1);
|
||||
}
|
||||
|
||||
|
|
@ -1177,7 +1177,7 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
|||
r.B(5) = s->B((base << (SHIFT + 2)) + 2); \
|
||||
r.B(6) = d->B((base << (SHIFT + 2)) + 3); \
|
||||
r.B(7) = s->B((base << (SHIFT + 2)) + 3); \
|
||||
XMM_ONLY( \
|
||||
ZMM_ONLY( \
|
||||
r.B(8) = d->B((base << (SHIFT + 2)) + 4); \
|
||||
r.B(9) = s->B((base << (SHIFT + 2)) + 4); \
|
||||
r.B(10) = d->B((base << (SHIFT + 2)) + 5); \
|
||||
|
|
@ -1199,7 +1199,7 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
|||
r.W(1) = s->W((base << (SHIFT + 1)) + 0); \
|
||||
r.W(2) = d->W((base << (SHIFT + 1)) + 1); \
|
||||
r.W(3) = s->W((base << (SHIFT + 1)) + 1); \
|
||||
XMM_ONLY( \
|
||||
ZMM_ONLY( \
|
||||
r.W(4) = d->W((base << (SHIFT + 1)) + 2); \
|
||||
r.W(5) = s->W((base << (SHIFT + 1)) + 2); \
|
||||
r.W(6) = d->W((base << (SHIFT + 1)) + 3); \
|
||||
|
|
@ -1215,14 +1215,14 @@ void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
|||
\
|
||||
r.L(0) = d->L((base << SHIFT) + 0); \
|
||||
r.L(1) = s->L((base << SHIFT) + 0); \
|
||||
XMM_ONLY( \
|
||||
ZMM_ONLY( \
|
||||
r.L(2) = d->L((base << SHIFT) + 1); \
|
||||
r.L(3) = s->L((base << SHIFT) + 1); \
|
||||
) \
|
||||
*d = r; \
|
||||
} \
|
||||
\
|
||||
XMM_ONLY( \
|
||||
ZMM_ONLY( \
|
||||
void glue(helper_punpck ## base_name ## qdq, SUFFIX)(CPUX86State \
|
||||
*env, \
|
||||
Reg *d, \
|
||||
|
|
@ -1405,32 +1405,32 @@ void glue(helper_phaddw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
|||
{
|
||||
d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1);
|
||||
d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3);
|
||||
XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5));
|
||||
XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7));
|
||||
ZMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5));
|
||||
ZMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7));
|
||||
d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1);
|
||||
d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3);
|
||||
XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5));
|
||||
XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7));
|
||||
ZMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5));
|
||||
ZMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7));
|
||||
}
|
||||
|
||||
void glue(helper_phaddd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
||||
{
|
||||
d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1);
|
||||
XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3));
|
||||
ZMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3));
|
||||
d->L((1 << SHIFT) + 0) = (uint32_t)((int32_t)s->L(0) + (int32_t)s->L(1));
|
||||
XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3));
|
||||
ZMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3));
|
||||
}
|
||||
|
||||
void glue(helper_phaddsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
||||
{
|
||||
d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1));
|
||||
d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3));
|
||||
XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5)));
|
||||
XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7)));
|
||||
ZMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5)));
|
||||
ZMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7)));
|
||||
d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1));
|
||||
d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3));
|
||||
XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5)));
|
||||
XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7)));
|
||||
ZMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5)));
|
||||
ZMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7)));
|
||||
}
|
||||
|
||||
void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
||||
|
|
@ -1459,32 +1459,32 @@ void glue(helper_phsubw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
|||
{
|
||||
d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1);
|
||||
d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3);
|
||||
XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5));
|
||||
XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7));
|
||||
ZMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5));
|
||||
ZMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7));
|
||||
d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1);
|
||||
d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3);
|
||||
XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5));
|
||||
XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7));
|
||||
ZMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5));
|
||||
ZMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7));
|
||||
}
|
||||
|
||||
void glue(helper_phsubd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
||||
{
|
||||
d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1);
|
||||
XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3));
|
||||
ZMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3));
|
||||
d->L((1 << SHIFT) + 0) = (uint32_t)((int32_t)s->L(0) - (int32_t)s->L(1));
|
||||
XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3));
|
||||
ZMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3));
|
||||
}
|
||||
|
||||
void glue(helper_phsubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
||||
{
|
||||
d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1));
|
||||
d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3));
|
||||
XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5)));
|
||||
XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7)));
|
||||
ZMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5)));
|
||||
ZMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7)));
|
||||
d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1));
|
||||
d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3));
|
||||
XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5)));
|
||||
XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7)));
|
||||
ZMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5)));
|
||||
ZMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7)));
|
||||
}
|
||||
|
||||
#define FABSB(_, x) (x > INT8_MAX ? -(int8_t)x : x)
|
||||
|
|
@ -1512,7 +1512,7 @@ void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
/* XXX could be checked during translation */
|
||||
if (shift >= (16 << SHIFT)) {
|
||||
r.Q(0) = 0;
|
||||
XMM_ONLY(r.Q(1) = 0);
|
||||
ZMM_ONLY(r.Q(1) = 0);
|
||||
} else {
|
||||
shift <<= 3;
|
||||
#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
|
||||
|
|
@ -1736,10 +1736,10 @@ void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
}
|
||||
}
|
||||
|
||||
d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
|
||||
d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status);
|
||||
d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status);
|
||||
d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status);
|
||||
d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
|
||||
d->ZMM_S(1) = float32_round_to_int(s->ZMM_S(1), &env->sse_status);
|
||||
d->ZMM_S(2) = float32_round_to_int(s->ZMM_S(2), &env->sse_status);
|
||||
d->ZMM_S(3) = float32_round_to_int(s->ZMM_S(3), &env->sse_status);
|
||||
|
||||
#if 0 /* TODO */
|
||||
if (mode & (1 << 3)) {
|
||||
|
|
@ -1774,8 +1774,8 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
}
|
||||
}
|
||||
|
||||
d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
|
||||
d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status);
|
||||
d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
|
||||
d->ZMM_D(1) = float64_round_to_int(s->ZMM_D(1), &env->sse_status);
|
||||
|
||||
#if 0 /* TODO */
|
||||
if (mode & (1 << 3)) {
|
||||
|
|
@ -1810,7 +1810,7 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
}
|
||||
}
|
||||
|
||||
d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
|
||||
d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
|
||||
|
||||
#if 0 /* TODO */
|
||||
if (mode & (1 << 3)) {
|
||||
|
|
@ -1845,7 +1845,7 @@ void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
}
|
||||
}
|
||||
|
||||
d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
|
||||
d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
|
||||
|
||||
#if 0 /* TODO */
|
||||
if (mode & (1 << 3)) {
|
||||
|
|
@ -1868,32 +1868,32 @@ void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
|
|||
|
||||
if (mask & (1 << 4)) {
|
||||
iresult = float32_add(iresult,
|
||||
float32_mul(d->XMM_S(0), s->XMM_S(0),
|
||||
float32_mul(d->ZMM_S(0), s->ZMM_S(0),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
if (mask & (1 << 5)) {
|
||||
iresult = float32_add(iresult,
|
||||
float32_mul(d->XMM_S(1), s->XMM_S(1),
|
||||
float32_mul(d->ZMM_S(1), s->ZMM_S(1),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
if (mask & (1 << 6)) {
|
||||
iresult = float32_add(iresult,
|
||||
float32_mul(d->XMM_S(2), s->XMM_S(2),
|
||||
float32_mul(d->ZMM_S(2), s->ZMM_S(2),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
if (mask & (1 << 7)) {
|
||||
iresult = float32_add(iresult,
|
||||
float32_mul(d->XMM_S(3), s->XMM_S(3),
|
||||
float32_mul(d->ZMM_S(3), s->ZMM_S(3),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero;
|
||||
d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero;
|
||||
d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero;
|
||||
d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero;
|
||||
d->ZMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero;
|
||||
d->ZMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero;
|
||||
d->ZMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero;
|
||||
d->ZMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero;
|
||||
}
|
||||
|
||||
void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
|
||||
|
|
@ -1902,18 +1902,18 @@ void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
|
|||
|
||||
if (mask & (1 << 4)) {
|
||||
iresult = float64_add(iresult,
|
||||
float64_mul(d->XMM_D(0), s->XMM_D(0),
|
||||
float64_mul(d->ZMM_D(0), s->ZMM_D(0),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
if (mask & (1 << 5)) {
|
||||
iresult = float64_add(iresult,
|
||||
float64_mul(d->XMM_D(1), s->XMM_D(1),
|
||||
float64_mul(d->ZMM_D(1), s->ZMM_D(1),
|
||||
&env->sse_status),
|
||||
&env->sse_status);
|
||||
}
|
||||
d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero;
|
||||
d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero;
|
||||
d->ZMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero;
|
||||
d->ZMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero;
|
||||
}
|
||||
|
||||
void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
||||
|
|
@ -2287,7 +2287,7 @@ void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
|||
#endif
|
||||
|
||||
#undef SHIFT
|
||||
#undef XMM_ONLY
|
||||
#undef ZMM_ONLY
|
||||
#undef Reg
|
||||
#undef B
|
||||
#undef W
|
||||
|
|
|
|||
|
|
@ -2948,10 +2948,10 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
|
|||
TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0;
|
||||
|
||||
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
|
||||
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, XMM_Q(0)));
|
||||
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
|
||||
tcg_gen_addi_tl(tcg_ctx, cpu_tmp0, cpu_A0, 8);
|
||||
tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
|
||||
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, XMM_Q(1)));
|
||||
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
|
||||
}
|
||||
|
||||
static inline void gen_sto_env_A0(DisasContext *s, int offset)
|
||||
|
|
@ -2962,10 +2962,10 @@ static inline void gen_sto_env_A0(DisasContext *s, int offset)
|
|||
TCGv cpu_A0 = *(TCGv *)tcg_ctx->cpu_A0;
|
||||
TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0;
|
||||
|
||||
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, XMM_Q(0)));
|
||||
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
|
||||
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
|
||||
tcg_gen_addi_tl(tcg_ctx, cpu_tmp0, cpu_A0, 8);
|
||||
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, XMM_Q(1)));
|
||||
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
|
||||
tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
|
||||
}
|
||||
|
||||
|
|
@ -3635,10 +3635,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
gen_lea_modrm(env, s, modrm);
|
||||
if (b1 & 1) {
|
||||
gen_stq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(0)));
|
||||
xmm_regs[reg].ZMM_L(0)));
|
||||
gen_op_st_v(s, MO_32, *cpu_T[0], cpu_A0);
|
||||
}
|
||||
break;
|
||||
|
|
@ -3705,29 +3705,29 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
|
||||
tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)));
|
||||
}
|
||||
break;
|
||||
case 0x310: /* movsd xmm, ea */
|
||||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
|
||||
}
|
||||
break;
|
||||
case 0x012: /* movlps */
|
||||
|
|
@ -3735,12 +3735,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
/* movhlps */
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(1)));
|
||||
}
|
||||
break;
|
||||
case 0x212: /* movsldup */
|
||||
|
|
@ -3749,40 +3749,40 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_L(2)));
|
||||
}
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
|
||||
break;
|
||||
case 0x312: /* movddup */
|
||||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
|
||||
}
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
|
||||
break;
|
||||
case 0x016: /* movhps */
|
||||
case 0x116: /* movhpd */
|
||||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(1)));
|
||||
xmm_regs[reg].ZMM_Q(1)));
|
||||
} else {
|
||||
/* movlhps */
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
|
||||
}
|
||||
break;
|
||||
case 0x216: /* movshdup */
|
||||
|
|
@ -3791,15 +3791,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_L(1)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_L(3)));
|
||||
}
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
|
||||
break;
|
||||
case 0x178:
|
||||
case 0x378:
|
||||
|
|
@ -3840,13 +3840,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
#ifdef TARGET_X86_64
|
||||
if (s->dflag == MO_64) {
|
||||
tcg_gen_ld_i64(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
|
||||
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
|
||||
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
|
||||
}
|
||||
break;
|
||||
|
|
@ -3854,13 +3854,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
|
||||
}
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)));
|
||||
break;
|
||||
case 0x7f: /* movq ea, mm */
|
||||
if (mod != 3) {
|
||||
|
|
@ -3890,23 +3890,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
case 0x211: /* movss ea, xmm */
|
||||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
||||
tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
|
||||
gen_op_st_v(s, MO_32, *cpu_T[0], cpu_A0);
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
|
||||
gen_op_movl(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
|
||||
}
|
||||
break;
|
||||
case 0x311: /* movsd ea, xmm */
|
||||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_stq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
|
||||
}
|
||||
break;
|
||||
case 0x013: /* movlps */
|
||||
|
|
@ -3914,7 +3914,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_stq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
goto illegal_op;
|
||||
}
|
||||
|
|
@ -3924,7 +3924,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_stq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(1)));
|
||||
xmm_regs[reg].ZMM_Q(1)));
|
||||
} else {
|
||||
goto illegal_op;
|
||||
}
|
||||
|
|
@ -3941,9 +3941,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
val = cpu_ldub_code(env, s->pc++);
|
||||
if (is_xmm) {
|
||||
tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
|
||||
tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], 0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(1)));
|
||||
op1_offset = offsetof(CPUX86State,xmm_t0);
|
||||
} else {
|
||||
tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val);
|
||||
|
|
@ -4064,10 +4064,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
if ((b >> 8) & 1) {
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0)));
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_Q(0)));
|
||||
} else {
|
||||
gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
|
||||
}
|
||||
op2_offset = offsetof(CPUX86State,xmm_t0);
|
||||
} else {
|
||||
|
|
@ -4099,7 +4099,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (b1) {
|
||||
val &= 7;
|
||||
tcg_gen_st16_tl(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_W(val)));
|
||||
} else {
|
||||
val &= 3;
|
||||
tcg_gen_st16_tl(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
|
|
@ -4116,7 +4116,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
val &= 7;
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
tcg_gen_ld16u_tl(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_W(val)));
|
||||
} else {
|
||||
val &= 3;
|
||||
rm = (modrm & 7);
|
||||
|
|
@ -4130,26 +4130,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (mod != 3) {
|
||||
gen_lea_modrm(env, s, modrm);
|
||||
gen_stq_env_A0(s, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(0)));
|
||||
xmm_regs[reg].ZMM_Q(0)));
|
||||
} else {
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(1)));
|
||||
}
|
||||
break;
|
||||
case 0x2d6: /* movq2dq */
|
||||
gen_helper_enter_mmx(tcg_ctx, cpu_env);
|
||||
rm = (modrm & 7);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
|
||||
offsetof(CPUX86State,fpregs[rm].mmx));
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
|
||||
gen_op_movq_env_0(tcg_ctx, offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)));
|
||||
break;
|
||||
case 0x3d6: /* movdq2q */
|
||||
gen_helper_enter_mmx(tcg_ctx, cpu_env);
|
||||
rm = (modrm & 7) | REX_B(s);
|
||||
gen_op_movq(tcg_ctx, offsetof(CPUX86State,fpregs[reg & 7].mmx),
|
||||
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
|
||||
offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
|
||||
break;
|
||||
case 0xd7: /* pmovmskb */
|
||||
case 0x1d7:
|
||||
|
|
@ -4201,20 +4201,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
|
||||
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
|
||||
gen_ldq_env_A0(s, op2_offset +
|
||||
offsetof(ZMMReg, XMM_Q(0)));
|
||||
offsetof(ZMMReg, ZMM_Q(0)));
|
||||
break;
|
||||
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
|
||||
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
|
||||
tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
|
||||
s->mem_index, MO_LEUL);
|
||||
tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env, op2_offset +
|
||||
offsetof(ZMMReg, XMM_L(0)));
|
||||
offsetof(ZMMReg, ZMM_L(0)));
|
||||
break;
|
||||
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
|
||||
tcg_gen_qemu_ld_tl(s->uc, cpu_tmp0, cpu_A0,
|
||||
s->mem_index, MO_LEUW);
|
||||
tcg_gen_st16_tl(tcg_ctx, cpu_tmp0, cpu_env, op2_offset +
|
||||
offsetof(ZMMReg, XMM_W(0)));
|
||||
offsetof(ZMMReg, ZMM_W(0)));
|
||||
break;
|
||||
case 0x2a: /* movntqda */
|
||||
gen_ldo_env_A0(s, op1_offset);
|
||||
|
|
@ -4639,7 +4639,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
switch (b) {
|
||||
case 0x14: /* pextrb */
|
||||
tcg_gen_ld8u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_B(val & 15)));
|
||||
xmm_regs[reg].ZMM_B(val & 15)));
|
||||
if (mod == 3) {
|
||||
gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]);
|
||||
} else {
|
||||
|
|
@ -4649,7 +4649,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
break;
|
||||
case 0x15: /* pextrw */
|
||||
tcg_gen_ld16u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_W(val & 7)));
|
||||
xmm_regs[reg].ZMM_W(val & 7)));
|
||||
if (mod == 3) {
|
||||
gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]);
|
||||
} else {
|
||||
|
|
@ -4661,7 +4661,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
if (ot == MO_32) { /* pextrd */
|
||||
tcg_gen_ld_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
|
||||
offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(val & 3)));
|
||||
xmm_regs[reg].ZMM_L(val & 3)));
|
||||
if (mod == 3) {
|
||||
tcg_gen_extu_i32_tl(tcg_ctx, *cpu_regs[rm], cpu_tmp2_i32);
|
||||
} else {
|
||||
|
|
@ -4672,7 +4672,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
#ifdef TARGET_X86_64
|
||||
tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
|
||||
offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(val & 1)));
|
||||
xmm_regs[reg].ZMM_Q(val & 1)));
|
||||
if (mod == 3) {
|
||||
tcg_gen_mov_i64(tcg_ctx, *cpu_regs[rm], cpu_tmp1_i64);
|
||||
} else {
|
||||
|
|
@ -4686,7 +4686,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
break;
|
||||
case 0x17: /* extractps */
|
||||
tcg_gen_ld32u_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(val & 3)));
|
||||
xmm_regs[reg].ZMM_L(val & 3)));
|
||||
if (mod == 3) {
|
||||
gen_op_mov_reg_v(tcg_ctx, ot, rm, *cpu_T[0]);
|
||||
} else {
|
||||
|
|
@ -4702,36 +4702,36 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
s->mem_index, MO_UB);
|
||||
}
|
||||
tcg_gen_st8_tl(tcg_ctx, *cpu_T[0], cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_B(val & 15)));
|
||||
xmm_regs[reg].ZMM_B(val & 15)));
|
||||
break;
|
||||
case 0x21: /* insertps */
|
||||
if (mod == 3) {
|
||||
tcg_gen_ld_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[rm]
|
||||
.XMM_L((val >> 6) & 3)));
|
||||
.ZMM_L((val >> 6) & 3)));
|
||||
} else {
|
||||
tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
|
||||
s->mem_index, MO_LEUL);
|
||||
}
|
||||
tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
|
||||
offsetof(CPUX86State,xmm_regs[reg]
|
||||
.XMM_L((val >> 4) & 3)));
|
||||
.ZMM_L((val >> 4) & 3)));
|
||||
if ((val >> 0) & 1)
|
||||
tcg_gen_st_i32(tcg_ctx, tcg_const_i32(tcg_ctx, 0 /*float32_zero*/),
|
||||
cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(0)));
|
||||
xmm_regs[reg].ZMM_L(0)));
|
||||
if ((val >> 1) & 1)
|
||||
tcg_gen_st_i32(tcg_ctx, tcg_const_i32(tcg_ctx, 0 /*float32_zero*/),
|
||||
cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(1)));
|
||||
xmm_regs[reg].ZMM_L(1)));
|
||||
if ((val >> 2) & 1)
|
||||
tcg_gen_st_i32(tcg_ctx, tcg_const_i32(tcg_ctx, 0 /*float32_zero*/),
|
||||
cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(2)));
|
||||
xmm_regs[reg].ZMM_L(2)));
|
||||
if ((val >> 3) & 1)
|
||||
tcg_gen_st_i32(tcg_ctx, tcg_const_i32(tcg_ctx, 0 /*float32_zero*/),
|
||||
cpu_env, offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(3)));
|
||||
xmm_regs[reg].ZMM_L(3)));
|
||||
break;
|
||||
case 0x22:
|
||||
if (ot == MO_32) { /* pinsrd */
|
||||
|
|
@ -4743,7 +4743,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
}
|
||||
tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
|
||||
offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_L(val & 3)));
|
||||
xmm_regs[reg].ZMM_L(val & 3)));
|
||||
} else { /* pinsrq */
|
||||
#ifdef TARGET_X86_64
|
||||
if (mod == 3) {
|
||||
|
|
@ -4754,7 +4754,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
}
|
||||
tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
|
||||
offsetof(CPUX86State,
|
||||
xmm_regs[reg].XMM_Q(val & 1)));
|
||||
xmm_regs[reg].ZMM_Q(val & 1)));
|
||||
#else
|
||||
goto illegal_op;
|
||||
#endif
|
||||
|
|
@ -4876,11 +4876,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
/* 32 bit access */
|
||||
gen_op_ld_v(s, MO_32, *cpu_T[0], cpu_A0);
|
||||
tcg_gen_st32_tl(tcg_ctx, *cpu_T[0], cpu_env,
|
||||
offsetof(CPUX86State,xmm_t0.XMM_L(0)));
|
||||
offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
|
||||
break;
|
||||
case 3:
|
||||
/* 64 bit access */
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_D(0)));
|
||||
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_D(0)));
|
||||
break;
|
||||
default:
|
||||
/* 128 bit access */
|
||||
|
|
|
|||
|
|
@ -276,8 +276,8 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
|
|||
{
|
||||
float64 *dst = (float64*)value;
|
||||
ZMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
||||
dst[0] = reg->XMM_D(0);
|
||||
dst[1] = reg->XMM_D(1);
|
||||
dst[0] = reg->ZMM_D(0);
|
||||
dst[1] = reg->ZMM_D(1);
|
||||
continue;
|
||||
}
|
||||
case UC_X86_REG_YMM0:
|
||||
|
|
@ -291,10 +291,10 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
|
|||
{
|
||||
float64 *dst = (float64*)value;
|
||||
ZMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
||||
dst[0] = reg->XMM_D(0);
|
||||
dst[1] = reg->XMM_D(1);
|
||||
dst[2] = reg->XMM_D(2);
|
||||
dst[3] = reg->XMM_D(3);
|
||||
dst[0] = reg->ZMM_D(0);
|
||||
dst[1] = reg->ZMM_D(1);
|
||||
dst[2] = reg->ZMM_D(2);
|
||||
dst[3] = reg->ZMM_D(3);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
|
@ -814,8 +814,8 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
|
|||
{
|
||||
float64 *src = (float64*)value;
|
||||
ZMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
||||
reg->XMM_D(0) = src[0];
|
||||
reg->XMM_D(1) = src[1];
|
||||
reg->ZMM_D(0) = src[0];
|
||||
reg->ZMM_D(1) = src[1];
|
||||
continue;
|
||||
}
|
||||
case UC_X86_REG_YMM0:
|
||||
|
|
@ -829,10 +829,10 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
|
|||
{
|
||||
float64 *src = (float64*)value;
|
||||
ZMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
|
||||
reg->XMM_D(4) = src[0];
|
||||
reg->XMM_D(5) = src[1];
|
||||
reg->XMM_D(6) = src[2];
|
||||
reg->XMM_D(7) = src[3];
|
||||
reg->ZMM_D(4) = src[0];
|
||||
reg->ZMM_D(5) = src[1];
|
||||
reg->ZMM_D(6) = src[2];
|
||||
reg->ZMM_D(7) = src[3];
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue