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target/arm: Make the t32 insn[25:23]=111 group non-overlapping

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The t32 decode has a group which represents a set of insns
which overlap with B_cond_thumb because they have [25:23]=111
(which is an invalid condition code field for the branch insn).
This group is currently defined using the {} overlap-OK syntax,
but it is almost entirely non-overlapping patterns. Switch
it over to use a non-overlapping group.

For this to be valid syntactically, CPS must move into the same
overlapping-group as the hint insns (CPS vs hints was the
only actual use of the overlap facility for the group).

The non-overlapping subgroup for CLREX/DSB/DMB/ISB/SB is no longer
necessary and so we can remove it (promoting those insns to
be members of the parent group).

Backports 45f11876ae86128bdee27e0b089045de43cc88e4
This commit is contained in:
Peter Maydell 2021-03-01 20:22:10 -05:00 committed by Lioncash
parent 666fe17025
commit 5680bc701b
1 changed files with 12 additions and 14 deletions

26
qemu/target/arm/t32.decode
View file

@ -296,8 +296,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
{ {
# Group insn[25:23] = 111, which is cond=111x for the branch below, # Group insn[25:23] = 111, which is cond=111x for the branch below,
# or unconditional, which would be illegal for the branch. # or unconditional, which would be illegal for the branch.
{ [
# Hints # Hints, and CPS
{ {
YIELD 1111 0011 1010 1111 1000 0000 0000 0001 YIELD 1111 0011 1010 1111 1000 0000 0000 0001
WFE 1111 0011 1010 1111 1000 0000 0000 0010 WFE 1111 0011 1010 1111 1000 0000 0000 0010
@ -310,20 +310,18 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
# The canonical nop ends in 0000 0000, but the whole rest # The canonical nop ends in 0000 0000, but the whole rest
# of the space is "reserved hint, behaves as nop". # of the space is "reserved hint, behaves as nop".
NOP 1111 0011 1010 1111 1000 0000 ---- ---- NOP 1111 0011 1010 1111 1000 0000 ---- ----
# If imod == '00' && M == '0' then SEE "Hint instructions", above.
CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
&cps
} }
# If imod == '00' && M == '0' then SEE "Hint instructions", above.
CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
&cps
# Miscellaneous control # Miscellaneous control
[ CLREX 1111 0011 1011 1111 1000 1111 0010 1111
CLREX 1111 0011 1011 1111 1000 1111 0010 1111 DSB 1111 0011 1011 1111 1000 1111 0100 ----
DSB 1111 0011 1011 1111 1000 1111 0100 ---- DMB 1111 0011 1011 1111 1000 1111 0101 ----
DMB 1111 0011 1011 1111 1000 1111 0101 ---- ISB 1111 0011 1011 1111 1000 1111 0110 ----
ISB 1111 0011 1011 1111 1000 1111 0110 ---- SB 1111 0011 1011 1111 1000 1111 0111 0000
SB 1111 0011 1011 1111 1000 1111 0111 0000
]
# Note that the v7m insn overlaps both the normal and banked insn. # Note that the v7m insn overlaps both the normal and banked insn.
{ {
@ -351,7 +349,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
HVC 1111 0111 1110 .... 1000 .... .... .... \ HVC 1111 0111 1110 .... 1000 .... .... .... \
&i imm=%imm16_16_0 &i imm=%imm16_16_0
UDF 1111 0111 1111 ---- 1010 ---- ---- ---- UDF 1111 0111 1111 ---- 1010 ---- ---- ----
} ]
B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21
} }