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target/mips: MXU: Add handler for an align instruction
Add translation handler for S32ALNI MXU instruction. Backports commit 79f5fee7a3c53494c7ca4bc18c72944f5e2d5c2f from qemu
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@ -25266,6 +25266,200 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
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}
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/*
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* MXU instruction category: align
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* S32ALN S32ALNI
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*/
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/*
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* S32ALNI XRc, XRb, XRa, optn3
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* Arrange bytes from XRb and XRc according to one of five sets of
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* rules determined by optn3, and place the result in XRa.
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+-----+---+-----+-------+-------+-------+-----------+
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* | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16|
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* +-----------+-----+---+-----+-------+-------+-------+-----------+
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*
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*/
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static void gen_mxu_S32ALNI(DisasContext *ctx)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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uint32_t optn3, pad, XRc, XRb, XRa;
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optn3 = extract32(ctx->opcode, 23, 3);
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pad = extract32(ctx->opcode, 21, 2);
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XRc = extract32(ctx->opcode, 14, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRa = extract32(ctx->opcode, 6, 4);
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if (unlikely(pad != 0)) {
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/* opcode padding incorrect -> do nothing */
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} else if (unlikely(XRa == 0)) {
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/* destination is zero register -> do nothing */
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} else if (unlikely((XRb == 0) && (XRc == 0))) {
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/* both operands zero registers -> just set destination to all 0s */
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], 0);
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} else if (unlikely(XRb == 0)) {
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/* XRb zero register -> just appropriatelly shift XRc into XRa */
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switch (optn3) {
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case MXU_OPTN3_PTN0:
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], 0);
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break;
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case MXU_OPTN3_PTN1:
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case MXU_OPTN3_PTN2:
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case MXU_OPTN3_PTN3:
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tcg_gen_shri_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRc - 1],
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8 * (4 - optn3));
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break;
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case MXU_OPTN3_PTN4:
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRc - 1]);
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break;
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}
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} else if (unlikely(XRc == 0)) {
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/* XRc zero register -> just appropriatelly shift XRb into XRa */
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switch (optn3) {
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case MXU_OPTN3_PTN0:
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRb - 1]);
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break;
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case MXU_OPTN3_PTN1:
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case MXU_OPTN3_PTN2:
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case MXU_OPTN3_PTN3:
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tcg_gen_shri_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRb - 1], 8 * optn3);
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break;
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case MXU_OPTN3_PTN4:
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], 0);
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break;
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}
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} else if (unlikely(XRb == XRc)) {
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/* both operands same -> just rotation or moving from any of them */
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switch (optn3) {
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case MXU_OPTN3_PTN0:
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case MXU_OPTN3_PTN4:
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRb - 1]);
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break;
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case MXU_OPTN3_PTN1:
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case MXU_OPTN3_PTN2:
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case MXU_OPTN3_PTN3:
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tcg_gen_rotli_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRb - 1], 8 * optn3);
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break;
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}
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} else {
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/* the most general case */
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switch (optn3) {
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case MXU_OPTN3_PTN0:
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{
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/* */
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/* XRb XRc */
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/* +---------------+ */
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/* | A B C D | E F G H */
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/* +-------+-------+ */
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/* | */
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/* XRa */
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/* */
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRb - 1]);
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}
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break;
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case MXU_OPTN3_PTN1:
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{
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/* */
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/* XRb XRc */
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/* +-------------------+ */
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/* A | B C D E | F G H */
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/* +---------+---------+ */
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/* | */
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/* XRa */
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/* */
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TCGv_i32 t0 = tcg_temp_new(tcg_ctx);
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TCGv_i32 t1 = tcg_temp_new(tcg_ctx);
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tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->mxu_gpr[XRb - 1], 0x00FFFFFF);
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tcg_gen_shli_i32(tcg_ctx, t0, t0, 8);
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tcg_gen_andi_i32(tcg_ctx, t1, tcg_ctx->mxu_gpr[XRc - 1], 0xFF000000);
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tcg_gen_shri_i32(tcg_ctx, t1, t1, 24);
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case MXU_OPTN3_PTN2:
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{
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/* */
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/* XRb XRc */
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/* +-------------------+ */
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/* A B | C D E F | G H */
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/* +---------+---------+ */
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/* | */
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/* XRa */
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/* */
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TCGv_i32 t0 = tcg_temp_new(tcg_ctx);
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TCGv_i32 t1 = tcg_temp_new(tcg_ctx);
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tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->mxu_gpr[XRb - 1], 0x0000FFFF);
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tcg_gen_shli_i32(tcg_ctx, t0, t0, 16);
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tcg_gen_andi_i32(tcg_ctx, t1, tcg_ctx->mxu_gpr[XRc - 1], 0xFFFF0000);
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tcg_gen_shri_i32(tcg_ctx, t1, t1, 16);
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case MXU_OPTN3_PTN3:
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{
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/* */
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/* XRb XRc */
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/* +-------------------+ */
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/* A B C | D E F G | H */
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/* +---------+---------+ */
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/* | */
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/* XRa */
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/* */
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TCGv_i32 t0 = tcg_temp_new(tcg_ctx);
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TCGv_i32 t1 = tcg_temp_new(tcg_ctx);
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tcg_gen_andi_i32(tcg_ctx, t0, tcg_ctx->mxu_gpr[XRb - 1], 0x000000FF);
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tcg_gen_shli_i32(tcg_ctx, t0, t0, 24);
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tcg_gen_andi_i32(tcg_ctx, t1, tcg_ctx->mxu_gpr[XRc - 1], 0xFFFFFF00);
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tcg_gen_shri_i32(tcg_ctx, t1, t1, 8);
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], t0, t1);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case MXU_OPTN3_PTN4:
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{
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/* */
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/* XRb XRc */
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/* +---------------+ */
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/* A B C D | E F G H | */
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/* +-------+-------+ */
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/* | */
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/* XRa */
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/* */
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->mxu_gpr[XRa - 1], tcg_ctx->mxu_gpr[XRc - 1]);
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}
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break;
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}
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}
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}
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/*
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* Decoding engine for MXU
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* =======================
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@ -25928,9 +26122,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
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generate_exception_end(ctx, EXCP_RI);
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break;
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case OPC_MXU_S32ALNI:
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/* TODO: Implement emulation of S32ALNI instruction. */
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MIPS_INVAL("OPC_MXU_S32ALNI");
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_S32ALNI(ctx);
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break;
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case OPC_MXU_S32LUI:
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/* TODO: Implement emulation of S32LUI instruction. */
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