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target/mips: Use env_cpu, env_archcpu

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Cleanup in the boilerplate that each target must define.
Replace mips_env_get_cpu with env_archcpu. The combination
CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Backports commit 5a7330b35cabc9e2fd3a8577b7004b63af8c57f3 from qemu
This commit is contained in:
Richard Henderson 2019-06-12 11:55:42 -04:00 committed by Lioncash
parent 585ba97389
commit 5790c1648d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
5 changed files with 18 additions and 34 deletions
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5
qemu/target/mips/cpu.h
View file

@ -1069,11 +1069,6 @@ struct MIPSCPU {
CPUMIPSState env;
};
static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
{
return container_of(env, MIPSCPU, env);
}
#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);

15
qemu/target/mips/helper.c
View file

@ -325,10 +325,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
void cpu_mips_tlb_flush(CPUMIPSState *env)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush(CPU(cpu));
tlb_flush(env_cpu(env));
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
@ -390,7 +388,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
#if defined(TARGET_MIPS64)
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
/* Access to at least one of the 64-bit segments has been disabled */
tlb_flush(CPU(mips_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
#endif
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
@ -437,7 +435,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int exception = 0, error_code = 0;
if (rw == MMU_INST_FETCH) {
@ -1382,8 +1380,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs;
CPUState *cs = env_cpu(env);
r4k_tlb_t *tlb;
target_ulong addr;
target_ulong end;
@ -1409,7 +1406,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
if (tlb->V0) {
cs = CPU(cpu);
addr = tlb->VPN & ~mask;
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@ -1423,7 +1419,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
}
}
if (tlb->V1) {
cs = CPU(cpu);
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@ -1444,7 +1439,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
int error_code,
uintptr_t pc)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
__func__, exception, error_code);

25
qemu/target/mips/op_helper.c
View file

@ -348,7 +348,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
int rw, uintptr_t retaddr)
{
hwaddr paddr;
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
paddr = cpu_mips_translate_address(env, address, rw);
@ -693,7 +693,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
return env;
}
cs = CPU(mips_env_get_cpu(env));
cs = env_cpu(env);
vpe_idx = tc_idx / cs->nr_threads;
*tc = tc_idx % cs->nr_threads;
other_cs = qemu_get_cpu(env->uc, vpe_idx);
@ -1292,7 +1292,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
MIPSCPU *cpu = env_archcpu(env);
env->active_tc.CP0_TCHalt = arg1 & 0x1;
@ -1308,7 +1308,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
MIPSCPU *other_cpu = mips_env_get_cpu(other);
MIPSCPU *other_cpu = env_archcpu(other);
// TODO: Halt TC / Restart (if allocated+active) TC.
@ -1421,7 +1421,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
tlb_flush(cs);
@ -1429,7 +1429,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
tlb_flush(cs);
@ -1437,7 +1437,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
tlb_flush(cs);
@ -1646,7 +1646,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* If the ASID changes, flush qemu's TLB. */
if ((old & env->CP0_EntryHi_ASID_mask) !=
(val & env->CP0_EntryHi_ASID_mask)) {
tlb_flush(CPU(mips_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
}
@ -1666,7 +1666,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
uint32_t val, old;
old = env->CP0_Status;
@ -1686,7 +1685,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default:
cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
}
}
@ -2475,8 +2474,6 @@ static void debug_pre_eret(CPUMIPSState *env)
static void debug_post_eret(CPUMIPSState *env)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
@ -2492,7 +2489,7 @@ static void debug_post_eret(CPUMIPSState *env)
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default:
cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
}
}
@ -2623,7 +2620,7 @@ void helper_pmon(CPUMIPSState *env, int function)
void helper_wait(CPUMIPSState *env)
{
CPUState *cs = CPU(mips_env_get_cpu(env));
CPUState *cs = env_cpu(env);
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);

3
qemu/target/mips/translate.c
View file

@ -30296,8 +30296,7 @@ void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong add
void cpu_state_reset(CPUMIPSState *env)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUState *cs = env_cpu(env);
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;

4
qemu/target/mips/translate_init.c
View file

@ -872,8 +872,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
switch (def->mmu_type) {
@ -890,7 +888,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
case MMU_TYPE_R6000:
case MMU_TYPE_R8000:
default:
cpu_abort(CPU(cpu), "MMU type not supported\n");
cpu_abort(env_cpu(env), "MMU type not supported\n");
}
}
#endif /* CONFIG_USER_ONLY */