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target-m68k: update CPU flags management

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Copied from target-i386

Backports commit 9fdb533fb129b19610941bd1e5dd93e7471a18f5 from qemu
This commit is contained in:
Laurent Vivier 2018-02-27 09:14:53 -05:00 committed by Lioncash
parent 125675e334
commit 57ea90a91f
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 104 additions and 41 deletions
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6
qemu/target-m68k/cpu.h
View file

@ -164,7 +164,7 @@ int cpu_m68k_exec(struct uc_struct *uc, CPUState *cpu);
int cpu_m68k_signal_handler(int host_signum, void *pinfo,
void *puc);
enum {
typedef enum {
CC_OP_DYNAMIC, /* Use env->cc_op */
CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
CC_OP_LOGICB, /* CC_DEST = result, CC_SRC = unused */
@ -185,7 +185,9 @@ enum {
CC_OP_SHIFTB, /* CC_DEST = result, CC_SRC = carry */
CC_OP_SHIFTW, /* CC_DEST = result, CC_SRC = carry */
CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
};
CC_OP_NB,
} CCOp;
#define CCF_C 0x01
#define CCF_V 0x02

139
qemu/target-m68k/translate.c
View file

@ -105,7 +105,7 @@ typedef struct DisasContext {
target_ulong insn_pc; /* Start of the current instruction. */
target_ulong pc;
int is_jmp;
int cc_op;
CCOp cc_op; /* Current CC operation */
int user;
uint32_t fpcr;
struct TranslationBlock *tb;
@ -145,6 +145,68 @@ typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
uint16_t insn)
#endif
enum {
USES_CC_DST = 1,
USES_CC_SRC = 2,
};
static const uint8_t cc_op_live[CC_OP_NB] = {
USES_CC_DST | USES_CC_SRC,
USES_CC_DST,
USES_CC_DST,
USES_CC_DST,
USES_CC_DST,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
USES_CC_DST | USES_CC_SRC,
};
static void set_cc_op(DisasContext *s, CCOp op)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int dead;
if (s->cc_op == op) {
return;
}
/* Discard CC computation that will no longer be used. */
dead = cc_op_live[s->cc_op] & ~cc_op_live[op];
if (dead & USES_CC_DST) {
tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST);
}
if (dead & USES_CC_SRC) {
tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_SRC);
}
if (s->cc_op == CC_OP_DYNAMIC) {
tcg_gen_discard_i32(tcg_ctx, tcg_ctx->QREG_CC_OP);
}
s->cc_op = op;
}
/* Update the CPU env CC_OP state. */
static inline void update_cc_op(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (s->cc_op != CC_OP_DYNAMIC) {
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_OP, s->cc_op);
}
}
/* Generate a load from the specified address. Narrow values are
sign extended to full register width. */
static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
@ -383,33 +445,31 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
return add;
}
/* Update the CPU env CC_OP state. */
static inline void gen_flush_cc_op(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (s->cc_op != CC_OP_DYNAMIC)
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_OP, s->cc_op);
}
/* Evaluate all the CC flags. */
static inline void gen_flush_flags(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (s->cc_op == CC_OP_FLAGS)
return;
gen_flush_cc_op(s);
gen_helper_flush_flags(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->cpu_env, tcg_ctx->QREG_CC_OP);
s->cc_op = CC_OP_FLAGS;
if (s->cc_op == CC_OP_DYNAMIC) {
gen_helper_flush_flags(tcg_ctx, tcg_ctx->QREG_CC_DEST,
tcg_ctx->cpu_env, tcg_ctx->QREG_CC_OP);
} else {
gen_helper_flush_flags(tcg_ctx, tcg_ctx->QREG_CC_DEST,
tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, s->cc_op));
}
set_cc_op(s, CC_OP_FLAGS);
}
#define SET_CC_OP(opsize, op) do { \
switch (opsize) { \
case OS_BYTE: \
s->cc_op = CC_OP_##op##B; break; \
set_cc_op(s, CC_OP_##op##B); break; \
case OS_WORD: \
s->cc_op = CC_OP_##op##W; break; \
set_cc_op(s, CC_OP_##op##W); break; \
case OS_LONG: \
s->cc_op = CC_OP_##op; break; \
set_cc_op(s, CC_OP_##op); break; \
default: \
abort(); \
} \
@ -705,7 +765,7 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
gen_flush_cc_op(s);
update_cc_op(s);
switch (cond) {
case 0: /* T */
tcg_gen_br(tcg_ctx, l1);
@ -824,7 +884,7 @@ DISAS_INSN(scc)
static void gen_lookup_tb(DisasContext *s)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_flush_cc_op(s);
update_cc_op(s);
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_PC, s->pc);
s->is_jmp = DISAS_UPDATE;
}
@ -833,7 +893,7 @@ static void gen_lookup_tb(DisasContext *s)
static void gen_jmp_im(DisasContext *s, uint32_t dest)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_flush_cc_op(s);
update_cc_op(s);
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
@ -842,7 +902,7 @@ static void gen_jmp_im(DisasContext *s, uint32_t dest)
static void gen_jmp(DisasContext *s, TCGv dest)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_flush_cc_op(s);
update_cc_op(s);
tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_PC, dest);
s->is_jmp = DISAS_JUMP;
}
@ -850,7 +910,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
static void gen_exception(DisasContext *s, uint32_t where, int nr)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
gen_flush_cc_op(s);
update_cc_op(s);
gen_jmp_im(s, where);
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, nr));
}
@ -972,7 +1032,7 @@ DISAS_INSN(divw)
tcg_gen_ext16u_i32(tcg_ctx, tmp, tcg_ctx->QREG_DIV1);
tcg_gen_shli_i32(tcg_ctx, src, tcg_ctx->QREG_DIV2, 16);
tcg_gen_or_i32(tcg_ctx, reg, tmp, src);
s->cc_op = CC_OP_FLAGS;
set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(divl)
@ -1005,7 +1065,7 @@ DISAS_INSN(divl)
/* rem */
tcg_gen_mov_i32 (tcg_ctx, reg, tcg_ctx->QREG_DIV2);
}
s->cc_op = CC_OP_FLAGS;
set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(addsub)
@ -1031,11 +1091,11 @@ DISAS_INSN(addsub)
if (add) {
tcg_gen_add_i32(tcg_ctx, dest, tmp, src);
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src);
s->cc_op = CC_OP_ADD;
set_cc_op(s, CC_OP_ADD);
} else {
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, tmp, src);
tcg_gen_sub_i32(tcg_ctx, dest, tmp, src);
s->cc_op = CC_OP_SUB;
set_cc_op(s, CC_OP_SUB);
}
gen_update_cc_add(s, dest, src);
if (insn & 0x100) {
@ -1228,7 +1288,6 @@ DISAS_INSN(bitop_im)
DEST_EA(env, insn, opsize, tmp, &addr);
}
}
DISAS_INSN(arith_im)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
@ -1256,14 +1315,14 @@ DISAS_INSN(arith_im)
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
tcg_gen_subi_i32(tcg_ctx, dest, dest, im);
gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im));
s->cc_op = CC_OP_SUB;
set_cc_op(s, CC_OP_SUB);
break;
case 3: /* addi */
tcg_gen_mov_i32(tcg_ctx, dest, src1);
tcg_gen_addi_i32(tcg_ctx, dest, dest, im);
gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im));
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, tcg_const_i32(tcg_ctx, im));
s->cc_op = CC_OP_ADD;
set_cc_op(s, CC_OP_ADD);
break;
case 5: /* eori */
tcg_gen_xori_i32(tcg_ctx, dest, src1, im);
@ -1273,7 +1332,7 @@ DISAS_INSN(arith_im)
tcg_gen_mov_i32(tcg_ctx, dest, src1);
tcg_gen_subi_i32(tcg_ctx, dest, dest, im);
gen_update_cc_add(s, dest, tcg_const_i32(tcg_ctx, im));
s->cc_op = CC_OP_SUB;
set_cc_op(s, CC_OP_SUB);
break;
default:
abort();
@ -1396,10 +1455,9 @@ DISAS_INSN(neg)
src1 = tcg_temp_new(tcg_ctx);
tcg_gen_mov_i32(tcg_ctx, src1, reg);
tcg_gen_neg_i32(tcg_ctx, reg, src1);
s->cc_op = CC_OP_SUB;
gen_update_cc_add(s, reg, src1);
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, tcg_const_i32(tcg_ctx, 0), src1);
s->cc_op = CC_OP_SUB;
set_cc_op(s, CC_OP_SUB);
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
@ -1410,6 +1468,7 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
if (!ccr_only) {
gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, val & 0xff00));
}
set_cc_op(s, CC_OP_FLAGS);
}
static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
@ -1654,11 +1713,11 @@ DISAS_INSN(addsubq)
if (insn & 0x0100) {
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
tcg_gen_subi_i32(tcg_ctx, dest, dest, val);
s->cc_op = CC_OP_SUB;
set_cc_op(s, CC_OP_SUB);
} else {
tcg_gen_addi_i32(tcg_ctx, dest, dest, val);
tcg_gen_setcond_i32(tcg_ctx, TCG_COND_LTU, tcg_ctx->QREG_CC_X, dest, src2);
s->cc_op = CC_OP_ADD;
set_cc_op(s, CC_OP_ADD);
}
gen_update_cc_add(s, dest, src2);
}
@ -1705,11 +1764,14 @@ DISAS_INSN(branch)
/* Bcc */
l1 = gen_new_label(tcg_ctx);
gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
update_cc_op(s);
gen_jmp_tb(s, 1, base + offset);
gen_set_label(tcg_ctx, l1);
update_cc_op(s);
gen_jmp_tb(s, 0, s->pc);
} else {
/* Unconditional branch. */
update_cc_op(s);
gen_jmp_tb(s, 0, base + offset);
}
}
@ -1897,7 +1959,6 @@ DISAS_INSN(addx)
reg = DREG(insn, 9);
src = DREG(insn, 0);
gen_helper_addx_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, src);
s->cc_op = CC_OP_FLAGS;
}
/* TODO: This could be implemented without helper functions. */
@ -1923,7 +1984,7 @@ DISAS_INSN(shift_im)
gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
}
}
s->cc_op = CC_OP_SHIFT;
set_cc_op(s, CC_OP_SHIFT);
}
DISAS_INSN(shift_reg)
@ -1945,7 +2006,7 @@ DISAS_INSN(shift_reg)
gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
}
}
s->cc_op = CC_OP_SHIFT;
set_cc_op(s, CC_OP_SHIFT);
}
DISAS_INSN(ff1)
@ -2779,7 +2840,7 @@ DISAS_INSN(macsr_to_ccr)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, 0);
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_DEST, tcg_ctx->QREG_MACSR, 0xf);
s->cc_op = CC_OP_FLAGS;
set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(to_mac)
@ -3156,20 +3217,20 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (!dc->is_jmp) {
gen_flush_cc_op(dc);
update_cc_op(dc);
tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_PC, dc->pc);
}
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, EXCP_DEBUG));
} else {
switch(dc->is_jmp) {
case DISAS_NEXT:
gen_flush_cc_op(dc);
update_cc_op(dc);
gen_jmp_tb(dc, 0, dc->pc);
break;
default:
case DISAS_JUMP:
case DISAS_UPDATE:
gen_flush_cc_op(dc);
update_cc_op(dc);
/* indicate that the hash table must be used to find the next TB */
tcg_gen_exit_tb(tcg_ctx, 0);
break;