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target/riscv: Convert quadrant 2 of RVXC insns to decodetree
Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
This commit is contained in:
Bastian Koppelmann
Lioncash
parent
b4854e3340
commit
580457a1d2
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@ -20,6 +20,7 @@
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%rd 7:5
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%rs1_3 7:3 !function=ex_rvc_register
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%rs2_3 2:3 !function=ex_rvc_register
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%rs2_5 2:5
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# Immediates:
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%imm_ci 12:s1 2:5
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@ -30,6 +31,10 @@
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%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
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%nzuimm_6bit 12:1 2:5
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%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
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%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
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%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
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%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
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%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
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%imm_lui 12:s1 2:5 !function=ex_shift_12
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@ -47,10 +52,15 @@
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&cj imm
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&c_shift shamt rd
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&c_ld uimm rd
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&c_sd uimm rs2
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&caddi16sp_lui imm_lui imm_addi16sp rd
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&cflwsp_ldsp uimm_flwsp uimm_ldsp rd
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&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2
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# Formats 16:
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@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
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@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
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@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
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@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
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@ -63,9 +73,19 @@
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@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
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@cj ... ........... .. &cj imm=%imm_cj
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@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
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@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
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@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
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@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
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@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
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@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
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uimm_ldsp=%uimm_6bit_ld %rd
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@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
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uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
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@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
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@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
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@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
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@ -96,3 +116,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2
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c_j 101 ........... 01 @cj
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c_beqz 110 ... ... ..... 01 @cb
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c_bnez 111 ... ... ..... 01 @cb
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# *** RV64C Standard Extension (Quadrant 2) ***
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c_slli 000 . ..... ..... 10 @c_shift2
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c_fldsp 001 . ..... ..... 10 @c_ld
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c_lwsp 010 . ..... ..... 10 @c_lw
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c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
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c_jr_mv 100 0 ..... ..... 10 @cr
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c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
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c_fsdsp 101 ...... ..... 10 @c_sd
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c_swsp 110 . ..... ..... 10 @c_sw
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c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
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@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
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arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
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return trans_bne(ctx, &arg);
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}
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static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
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{
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int shamt = a->shamt;
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if (shamt == 0) {
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/* For RV128 a shamt of 0 means a shift by 64 */
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shamt = 64;
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}
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/* Ensure, that shamt[5] is zero for RV32 */
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if (shamt >= TARGET_LONG_BITS) {
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return false;
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}
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arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
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return trans_slli(ctx, &arg);
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}
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static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
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{
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arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
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return trans_fld(ctx, &arg);
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}
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static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
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{
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arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
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return trans_lw(ctx, &arg);
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}
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static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FLWSP */
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arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
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return trans_flw(ctx, &arg_flw);
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#else
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/* C.LDSP */
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arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
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return trans_ld(ctx, &arg_ld);
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#endif
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return false;
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}
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static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
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{
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if (a->rd != 0 && a->rs2 == 0) {
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/* C.JR */
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arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
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return trans_jalr(ctx, &arg);
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} else if (a->rd != 0 && a->rs2 != 0) {
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/* C.MV */
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arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
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return trans_add(ctx, &arg);
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}
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return false;
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}
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static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
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{
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if (a->rd == 0 && a->rs2 == 0) {
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/* C.EBREAK */
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arg_ebreak arg = { };
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return trans_ebreak(ctx, &arg);
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} else if (a->rd != 0) {
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if (a->rs2 == 0) {
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/* C.JALR */
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arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
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return trans_jalr(ctx, &arg);
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} else {
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/* C.ADD */
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arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
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return trans_add(ctx, &arg);
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}
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}
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return false;
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}
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static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
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{
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arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
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return trans_fsd(ctx, &arg);
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}
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static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
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{
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arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
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return trans_sw(ctx, &arg);
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}
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static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
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{
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#ifdef TARGET_RISCV32
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/* C.FSWSP */
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arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
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return trans_fsw(ctx, &a_fsw);
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#else
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/* C.SDSP */
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arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
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return trans_sd(ctx, &a_sd);
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#endif
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}
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@ -703,6 +703,7 @@ static void mark_fs_dirty(DisasContext *ctx)
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static inline void mark_fs_dirty(DisasContext *ctx) { }
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#endif
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#if !defined(TARGET_RISCV64)
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static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
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int rs1, target_long imm)
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{
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@ -779,6 +780,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
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tcg_temp_free(tcg_ctx, t0);
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}
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#endif
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static void gen_set_rm(DisasContext *ctx, int rm)
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{
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@ -855,84 +857,6 @@ static void decode_RV32_64C0(DisasContext *ctx)
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}
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}
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static void decode_RV32_64C2(DisasContext *ctx)
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{
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uint8_t rd, rs2;
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uint8_t funct3 = extract32(ctx->opcode, 13, 3);
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rd = GET_RD(ctx->opcode);
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switch (funct3) {
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case 0: /* C.SLLI -> slli rd, rd, shamt[5:0]
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C.SLLI64 -> */
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gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode));
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break;
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case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */
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gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
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break;
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case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */
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gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
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break;
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case 3:
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#if defined(TARGET_RISCV64)
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/* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */
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gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode));
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#else
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/* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */
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gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode));
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#endif
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break;
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case 4:
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rs2 = GET_C_RS2(ctx->opcode);
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if (extract32(ctx->opcode, 12, 1) == 0) {
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if (rs2 == 0) {
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/* C.JR -> jalr x0, rs1, 0*/
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gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
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} else {
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/* C.MV -> add rd, x0, rs2 */
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gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
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}
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} else {
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if (rd == 0) {
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/* C.EBREAK -> ebreak*/
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gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
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} else {
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if (rs2 == 0) {
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/* C.JALR -> jalr x1, rs1, 0*/
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gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
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} else {
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/* C.ADD -> add rd, rd, rs2 */
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gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
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}
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}
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}
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break;
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case 5:
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/* C.FSDSP -> fsd rs2, offset[8:3](x2)*/
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gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode),
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GET_C_SDSP_IMM(ctx->opcode));
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/* C.SQSP */
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break;
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case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/
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gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode),
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GET_C_SWSP_IMM(ctx->opcode));
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break;
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case 7:
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#if defined(TARGET_RISCV64)
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/* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/
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gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode),
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GET_C_SDSP_IMM(ctx->opcode));
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#else
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/* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */
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gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode),
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GET_C_SWSP_IMM(ctx->opcode));
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#endif
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break;
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}
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}
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static void decode_RV32_64C(DisasContext *ctx)
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{
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uint8_t op = extract32(ctx->opcode, 0, 2);
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@ -941,9 +865,6 @@ static void decode_RV32_64C(DisasContext *ctx)
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case 0:
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decode_RV32_64C0(ctx);
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break;
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case 2:
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decode_RV32_64C2(ctx);
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break;
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}
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}
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