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target/arm: Implement writing to CONTROL_NS for v8M

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In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.

Backports commit 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f from qemu
This commit is contained in:
Peter Maydell 2018-03-08 09:37:53 -05:00 committed by Lioncash
parent 09cfe29d5b
commit 5812f7e3a3
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 0 deletions
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10
qemu/target/arm/helper.c
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@ -9681,6 +9681,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
}
env->v7m.faultmask[M_REG_NS] = val & 1;
return;
case 0x94: /* CONTROL_NS */
if (!env->v7m.secure) {
return;
}
write_v7m_control_spsel_for_secstate(env,
val & R_V7M_CONTROL_SPSEL_MASK,
M_REG_NS);
env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
return;
case 0x98: /* SP_NS */
{
/* This gives the non-secure SP selected based on whether we're