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tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32

Browse source 
Rather than allow arbitrary shift+trunc, only concern ourselves
with low and high parts. This is all that was being used anyway.

Backports commit 609ad70562793937257c89d07bf7c1370b9fc9aa from qemu
This commit is contained in:
Richard Henderson 2018-02-10 22:57:27 -05:00 committed by Lioncash
parent a05256b206
commit 58e939b91f
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
26 changed files with 97 additions and 69 deletions
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3
qemu/aarch64.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_aarch64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64

3
qemu/aarch64eb.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64eb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64eb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64eb
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_aarch64eb
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64eb
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64eb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64eb

3
qemu/arm.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_arm
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_arm
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_arm
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_arm
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_arm
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_arm
#define tcg_gen_xor_i32 tcg_gen_xor_i32_arm
#define tcg_gen_xor_i64 tcg_gen_xor_i64_arm
#define tcg_gen_xori_i32 tcg_gen_xori_i32_arm

3
qemu/armeb.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_armeb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_armeb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_armeb
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_armeb
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_armeb
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_armeb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_armeb

3
qemu/header_gen.py
View file

@ -2746,6 +2746,8 @@ symbols = (
'tcg_gen_ext_i32_i64',
'tcg_gen_extr32_i64',
'tcg_gen_extr_i64_i32',
'tcg_gen_extrh_i64_i32',
'tcg_gen_extrl_i64_i32',
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
'tcg_gen_ld16s_i64',
@ -2851,7 +2853,6 @@ symbols = (
'tcg_gen_subi_i32',
'tcg_gen_subi_i64',
'tcg_gen_trunc_i64_i32',
'tcg_gen_trunc_shr_i64_i32',
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
'tcg_gen_xori_i32',

3
qemu/m68k.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_m68k
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_m68k
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_m68k
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_m68k
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_m68k
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_m68k
#define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k
#define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k
#define tcg_gen_xori_i32 tcg_gen_xori_i32_m68k

3
qemu/mips.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips

3
qemu/mips64.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64

3
qemu/mips64el.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64el
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64el
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64el
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mips64el
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64el
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64el
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64el

3
qemu/mipsel.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mipsel
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mipsel
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mipsel
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_mipsel
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mipsel
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mipsel
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mipsel

3
qemu/powerpc.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_powerpc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_powerpc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_powerpc
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_powerpc
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_powerpc
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_powerpc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_powerpc

3
qemu/sparc.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_sparc
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc

3
qemu/sparc64.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_sparc64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc64

14
qemu/tcg/README
View file

@ -314,11 +314,17 @@ This operation would be equivalent to
dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
* trunc_shr_i64_i32 t0, t1, pos
* extrl_i64_i32 t0, t1
For 64-bit hosts only, right shift the 64-bit input T1 by POS and
truncate to 32-bit output T0. Depending on the host, this may be
a simple mov/shift, or may require additional canonicalization.
For 64-bit hosts only, extract the low 32-bits of input T1 and place it
into 32-bit output T0. Depending on the host, this may be a simple move,
or may require additional canonicalization.
* extrh_i64_i32 t0, t1
For 64-bit hosts only, extract the high 32-bits of input T1 and place it
into 32-bit output T0. Depending on the host, this may be a simple shift,
or may require additional canonicalization.
********* Conditional moves

3
qemu/tcg/aarch64/tcg-target.h
View file

@ -69,7 +69,8 @@ typedef enum {
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1

3
qemu/tcg/i386/tcg-target.h
View file

@ -101,7 +101,8 @@ extern bool have_bmi1;
#define TCG_TARGET_HAS_mulsh_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div2_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1

18
qemu/tcg/optimize.c
View file

@ -293,7 +293,6 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
case INDEX_op_shr_i32:
return (uint32_t)x >> (y & 31);
case INDEX_op_trunc_shr_i64_i32:
case INDEX_op_shr_i64:
return (uint64_t)x >> (y & 63);
@ -897,8 +896,11 @@ void tcg_optimize(TCGContext *s)
}
break;
case INDEX_op_trunc_shr_i64_i32:
mask = (uint64_t)temps[args[1]].mask >> args[2];
case INDEX_op_extrl_i64_i32:
mask = (uint32_t)temps[args[1]].mask;
break;
case INDEX_op_extrh_i64_i32:
mask = (uint64_t)temps[args[1]].mask >> 32;
break;
CASE_OP_32_64(shl):
@ -1040,6 +1042,8 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
if (temp_is_const(s, args[1])) {
tmp = do_constant_folding(s, opc, temps[args[1]].val, 0);
tcg_opt_gen_movi(s, op, args, args[0], tmp);
@ -1047,14 +1051,6 @@ void tcg_optimize(TCGContext *s)
}
goto do_default;
case INDEX_op_trunc_shr_i64_i32:
if (temp_is_const(s, args[1])) {
tmp = do_constant_folding(s, opc, temps[args[1]].val, args[2]);
tcg_opt_gen_movi(s, op, args, args[0], tmp);
break;
}
goto do_default;
CASE_OP_32_64(add):
CASE_OP_32_64(sub):
CASE_OP_32_64(mul):

3
qemu/tcg/ppc/tcg-target.h
View file

@ -76,7 +76,8 @@ typedef enum {
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_rot_i64 1

3
qemu/tcg/s390/tcg-target.h
View file

@ -71,7 +71,8 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div2_i64 1
#define TCG_TARGET_HAS_rot_i64 1

14
qemu/tcg/sparc/tcg-target.c
View file

@ -1415,12 +1415,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32u_i64:
tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
break;
case INDEX_op_trunc_shr_i64_i32:
if (a2 == 0) {
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
} else {
tcg_out_arithi(s, a0, a1, a2, SHIFT_SRLX);
}
case INDEX_op_extrl_i64_i32:
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
break;
case INDEX_op_extrh_i64_i32:
tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
break;
case INDEX_op_brcond_i64:
@ -1537,7 +1536,8 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ext32u_i64, { "R", "R" } },
{ INDEX_op_ext_i32_i64, { "R", "r" } },
{ INDEX_op_extu_i32_i64, { "R", "r" } },
{ INDEX_op_trunc_shr_i64_i32, { "r", "R" } },
{ INDEX_op_extrl_i64_i32, { "r", "R" } },
{ INDEX_op_extrh_i64_i32, { "r", "R" } },
{ INDEX_op_brcond_i64, { "RZ", "RJ" } },
{ INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },

3
qemu/tcg/sparc/tcg-target.h
View file

@ -117,7 +117,8 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_trunc_shr_i64_i32 1
#define TCG_TARGET_HAS_extrl_i64_i32 1
#define TCG_TARGET_HAS_extrh_i64_i32 1
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_rot_i64 0

47
qemu/tcg/tcg-op.c
View file

@ -1738,30 +1738,31 @@ void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, T
/* Size changing operations. */
void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, unsigned count)
void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg)
{
tcg_debug_assert(count < 64);
if (TCG_TARGET_REG_BITS == 32) {
if (count >= 32) {
tcg_gen_shri_i32(s, ret, TCGV_HIGH(arg), count - 32);
} else if (count == 0) {
tcg_gen_mov_i32(s, ret, TCGV_LOW(arg));
} else {
TCGv_i64 t = tcg_temp_new_i64(s);
tcg_gen_shri_i64(s, t, arg, count);
tcg_gen_mov_i32(s, ret, TCGV_LOW(t));
tcg_temp_free_i64(s, t);
}
} else if (TCG_TARGET_HAS_trunc_shr_i64_i32) {
tcg_gen_op3i_i32(s, INDEX_op_trunc_shr_i64_i32, ret,
MAKE_TCGV_I32(GET_TCGV_I64(arg)), count);
} else if (count == 0) {
tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
tcg_gen_mov_i32(s, ret, TCGV_LOW(arg));
} else if (TCG_TARGET_HAS_extrl_i64_i32) {
tcg_gen_op2(s, INDEX_op_extrl_i64_i32,
GET_TCGV_I32(ret), GET_TCGV_I64(arg));
} else {
TCGv_i64 t = tcg_temp_new_i64(s);
tcg_gen_shri_i64(s, t, arg, count);
tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(t)));
tcg_temp_free_i64(s, t);
tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
}
}
void tcg_gen_extrh_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg)
{
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_mov_i32(s, ret, TCGV_HIGH(arg));
} else if (TCG_TARGET_HAS_extrh_i64_i32) {
tcg_gen_op2(s, INDEX_op_extrh_i64_i32,
GET_TCGV_I32(ret), GET_TCGV_I64(arg));
} else {
TCGv_i64 t = tcg_temp_new_i64(s);
tcg_gen_shri_i64(s, t, arg, 32);
tcg_gen_mov_i32(s, ret, MAKE_TCGV_I32(GET_TCGV_I64(t)));
tcg_temp_free_i64(s, t);
}
}
@ -1819,8 +1820,8 @@ void tcg_gen_extr_i64_i32(TCGContext *s, TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg)
tcg_gen_mov_i32(s, lo, TCGV_LOW(arg));
tcg_gen_mov_i32(s, hi, TCGV_HIGH(arg));
} else {
tcg_gen_trunc_shr_i64_i32(s, lo, arg, 0);
tcg_gen_trunc_shr_i64_i32(s, hi, arg, 32);
tcg_gen_extrl_i64_i32(s, lo, arg);
tcg_gen_extrh_i64_i32(s, hi, arg);
}
}

5
qemu/tcg/tcg-op.h
View file

@ -684,7 +684,8 @@ static inline void tcg_gen_neg_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg)
void tcg_gen_extu_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg);
void tcg_gen_ext_i32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i32 arg);
void tcg_gen_concat_i32_i64(TCGContext *s, TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
void tcg_gen_trunc_shr_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg, unsigned int c);
void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg);
void tcg_gen_extrh_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg);
void tcg_gen_extr_i64_i32(TCGContext *s, TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
void tcg_gen_extr32_i64(TCGContext *s, TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
@ -695,7 +696,7 @@ static inline void tcg_gen_concat32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 lo
static inline void tcg_gen_trunc_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg)
{
tcg_gen_trunc_shr_i64_i32(s, ret, arg, 0);
tcg_gen_extrl_i64_i32(s, ret, arg);
}
/* QEMU specific operations. */

8
qemu/tcg/tcg-opc.h
View file

@ -146,9 +146,13 @@ DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
DEF(extu_i32_i64, 1, 1, 0, IMPL64)
DEF(trunc_shr_i64_i32, 1, 1, 1,
IMPL(TCG_TARGET_HAS_trunc_shr_i64_i32)
DEF(extrl_i64_i32, 1, 1, 0,
IMPL(TCG_TARGET_HAS_extrl_i64_i32)
| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
DEF(extrh_i64_i32, 1, 1, 0,
IMPL(TCG_TARGET_HAS_extrh_i64_i32)
| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))

3
qemu/tcg/tcg.h
View file

@ -67,7 +67,8 @@ typedef uint64_t TCGRegSet;
#if TCG_TARGET_REG_BITS == 32
/* Turn some undef macros into false macros. */
#define TCG_TARGET_HAS_trunc_shr_i64_i32 0
#define TCG_TARGET_HAS_extrl_i64_i32 0
#define TCG_TARGET_HAS_extrh_i64_i32 0
#define TCG_TARGET_HAS_div_i64 0
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_div2_i64 0

3
qemu/x86_64.h
View file

@ -2740,6 +2740,8 @@
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_x86_64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_x86_64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_x86_64
#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_x86_64
#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
@ -2845,7 +2847,6 @@
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_x86_64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_x86_64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_x86_64