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target/arm: Clear SVE high bits for FMOV

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Use write_fp_dreg and clear_vec_high to zero the bits
that need zeroing for these cases.

Backports commit 9a9f1f59521f46e8ff4527d9a2b52f83577e2aa3 from qemu
This commit is contained in:
Richard Henderson 2018-05-14 08:43:51 -04:00 committed by Lioncash
parent 67740bbc7f
commit 5902f32abf
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 5 additions and 12 deletions
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17
qemu/target/arm/translate-a64.c
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@ -5783,31 +5783,24 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
if (itof) {
TCGv_i64 tcg_rn = cpu_reg(s, rn);
TCGv_i64 tmp;
switch (type) {
case 0:
{
/* 32 bit */
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
tmp = tcg_temp_new_i64(tcg_ctx);
tcg_gen_ext32u_i64(tcg_ctx, tmp, tcg_rn);
tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_offset(s, rd, MO_64));
tcg_gen_movi_i64(tcg_ctx, tmp, 0);
tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
write_fp_dreg(s, rd, tmp);
tcg_temp_free_i64(tcg_ctx, tmp);
break;
}
case 1:
{
/* 64 bit */
TCGv_i64 tmp = tcg_const_i64(tcg_ctx, 0);
tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_offset(s, rd, MO_64));
tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
tcg_temp_free_i64(tcg_ctx, tmp);
write_fp_dreg(s, rd, tcg_rn);
break;
}
case 2:
/* 64 bit to top half. */
tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
clear_vec_high(s, true, rd);
break;
}
} else {