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target/arm: Synchronize with qemu
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@ -6055,17 +6055,20 @@ static void gen_shr64_ins_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t shi
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static void gen_shr_ins_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
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{
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uint64_t mask = (2ull << ((8 << vece) - 1)) - 1;
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TCGv_vec t = tcg_temp_new_vec_matching(s, d);
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TCGv_vec m = tcg_temp_new_vec_matching(s, d);
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if (sh == 0) {
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tcg_gen_mov_vec(s, d, a);
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} else {
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TCGv_vec t = tcg_temp_new_vec_matching(s, d);
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TCGv_vec m = tcg_temp_new_vec_matching(s, d);
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tcg_gen_dupi_vec(s, vece, m, mask ^ (mask >> sh));
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tcg_gen_shri_vec(s, vece, t, a, sh);
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tcg_gen_and_vec(s, vece, d, d, m);
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tcg_gen_or_vec(s, vece, d, d, t);
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tcg_gen_dupi_vec(s, vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh));
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tcg_gen_shri_vec(s, vece, t, a, sh);
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tcg_gen_and_vec(s, vece, d, d, m);
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tcg_gen_or_vec(s, vece, d, d, t);
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tcg_temp_free_vec(s, t);
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tcg_temp_free_vec(s, m);
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tcg_temp_free_vec(s, t);
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tcg_temp_free_vec(s, m);
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}
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}
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const GVecGen2i sri_op[4] = {
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@ -10360,7 +10363,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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}
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/* Perform base writeback before the loaded value to
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ensure correct behavior with overlapping index registers.
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ldrd with base writeback is is undefined if the
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ldrd with base writeback is undefined if the
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destination and index registers overlap. */
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if (!pbit) {
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gen_add_datah_offset(s, insn, address_offset, addr);
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@ -13941,29 +13944,28 @@ static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
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log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size,
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dc->thumb | (dc->sctlr_b << 1));
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log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size);
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#endif
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}
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static const TranslatorOps arm_translator_ops = {
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arm_tr_init_disas_context,
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arm_tr_tb_start,
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arm_tr_insn_start,
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arm_tr_breakpoint_check,
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arm_tr_translate_insn,
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arm_tr_tb_stop,
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arm_tr_disas_log,
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.init_disas_context = arm_tr_init_disas_context,
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.tb_start = arm_tr_tb_start,
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.insn_start = arm_tr_insn_start,
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.breakpoint_check = arm_tr_breakpoint_check,
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.translate_insn = arm_tr_translate_insn,
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.tb_stop = arm_tr_tb_stop,
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.disas_log = arm_tr_disas_log,
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};
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static const TranslatorOps thumb_translator_ops = {
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arm_tr_init_disas_context,
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arm_tr_tb_start,
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arm_tr_insn_start,
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arm_tr_breakpoint_check,
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thumb_tr_translate_insn,
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arm_tr_tb_stop,
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arm_tr_disas_log,
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.init_disas_context = arm_tr_init_disas_context,
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.tb_start = arm_tr_tb_start,
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.insn_start = arm_tr_insn_start,
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.breakpoint_check = arm_tr_breakpoint_check,
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.translate_insn = thumb_tr_translate_insn,
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.tb_stop = arm_tr_tb_stop,
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.disas_log = arm_tr_disas_log,
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};
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/* generate intermediate code for basic block 'tb'. */
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