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target/riscv: fpu_helper: Match function defs in HELPER macros

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Update the function definitions generated in helper.h to match the
actual function implementations.

Also remove all compile time XLEN checks when building.

Backports 5b6c291b8db8effff625db321be232e0c4dcdb6c
This commit is contained in:
Alistair Francis 2021-03-08 15:22:33 -05:00 committed by Lioncash
parent b23e786779
commit 5973588ac0
5 changed files with 32 additions and 24 deletions
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8
qemu/header_gen.py
View file

@ -6223,10 +6223,18 @@ riscv_symbols = (
'helper_fadd_s',
'helper_fclass_d',
'helper_fclass_s',
'helper_fcvt_d_l',
'helper_fcvt_d_lu',
'helper_fcvt_d_s',
'helper_fcvt_d_w',
'helper_fcvt_d_wu',
'helper_fcvt_l_d',
'helper_fcvt_l_s',
'helper_fcvt_lu_d',
'helper_fcvt_lu_s',
'helper_fcvt_s_d',
'helper_fcvt_s_l',
'helper_fcvt_s_lu',
'helper_fcvt_s_w',
'helper_fcvt_s_wu',
'helper_fcvt_w_d',

8
qemu/riscv32.h
View file

@ -3659,10 +3659,18 @@
#define helper_fadd_s helper_fadd_s_riscv32
#define helper_fclass_d helper_fclass_d_riscv32
#define helper_fclass_s helper_fclass_s_riscv32
#define helper_fcvt_d_l helper_fcvt_d_l_riscv32
#define helper_fcvt_d_lu helper_fcvt_d_lu_riscv32
#define helper_fcvt_d_s helper_fcvt_d_s_riscv32
#define helper_fcvt_d_w helper_fcvt_d_w_riscv32
#define helper_fcvt_d_wu helper_fcvt_d_wu_riscv32
#define helper_fcvt_l_d helper_fcvt_l_d_riscv32
#define helper_fcvt_l_s helper_fcvt_l_s_riscv32
#define helper_fcvt_lu_d helper_fcvt_lu_d_riscv32
#define helper_fcvt_lu_s helper_fcvt_lu_s_riscv32
#define helper_fcvt_s_d helper_fcvt_s_d_riscv32
#define helper_fcvt_s_l helper_fcvt_s_l_riscv32
#define helper_fcvt_s_lu helper_fcvt_s_lu_riscv32
#define helper_fcvt_s_w helper_fcvt_s_w_riscv32
#define helper_fcvt_s_wu helper_fcvt_s_wu_riscv32
#define helper_fcvt_w_d helper_fcvt_w_d_riscv32

8
qemu/riscv64.h
View file

@ -3659,10 +3659,18 @@
#define helper_fadd_s helper_fadd_s_riscv64
#define helper_fclass_d helper_fclass_d_riscv64
#define helper_fclass_s helper_fclass_s_riscv64
#define helper_fcvt_d_l helper_fcvt_d_l_riscv64
#define helper_fcvt_d_lu helper_fcvt_d_lu_riscv64
#define helper_fcvt_d_s helper_fcvt_d_s_riscv64
#define helper_fcvt_d_w helper_fcvt_d_w_riscv64
#define helper_fcvt_d_wu helper_fcvt_d_wu_riscv64
#define helper_fcvt_l_d helper_fcvt_l_d_riscv64
#define helper_fcvt_l_s helper_fcvt_l_s_riscv64
#define helper_fcvt_lu_d helper_fcvt_lu_d_riscv64
#define helper_fcvt_lu_s helper_fcvt_lu_s_riscv64
#define helper_fcvt_s_d helper_fcvt_s_d_riscv64
#define helper_fcvt_s_l helper_fcvt_s_l_riscv64
#define helper_fcvt_s_lu helper_fcvt_s_lu_riscv64
#define helper_fcvt_s_w helper_fcvt_s_w_riscv64
#define helper_fcvt_s_wu helper_fcvt_s_wu_riscv64
#define helper_fcvt_w_d helper_fcvt_w_d_riscv64

8
qemu/target/riscv/fpu_helper.c
View file

@ -223,7 +223,6 @@ target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
return (int32_t)float32_to_uint32(frs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
{
float32 frs1 = check_nanbox_s(rs1);
@ -235,7 +234,6 @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
float32 frs1 = check_nanbox_s(rs1);
return float32_to_uint64(frs1, &env->fp_status);
}
#endif
uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
{
@ -247,7 +245,6 @@ uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
{
return nanbox_s(int64_to_float32(rs1, &env->fp_status));
@ -257,7 +254,6 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
{
return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
}
#endif
target_ulong helper_fclass_s(uint64_t rs1)
{
@ -336,7 +332,6 @@ target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
return (int32_t)float64_to_uint32(frs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_int64(frs1, &env->fp_status);
@ -346,7 +341,6 @@ uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
{
return float64_to_uint64(frs1, &env->fp_status);
}
#endif
uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
{
@ -358,7 +352,6 @@ uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
return uint32_to_float64((uint32_t)rs1, &env->fp_status);
}
#if defined(TARGET_RISCV64)
uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
{
return int64_to_float64(rs1, &env->fp_status);
@ -368,7 +361,6 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
{
return uint64_to_float64(rs1, &env->fp_status);
}
#endif
target_ulong helper_fclass_d(uint64_t frs1)
{

24
qemu/target/riscv/helper.h
View file

@ -30,16 +30,12 @@ DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64)
#endif
DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64)
/* Floating Point - Double Precision */
@ -57,16 +53,12 @@ DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64)
#endif
DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Special functions */