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target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs

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In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Backports commit 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8 from qemu
This commit is contained in:
Artyom Tarasenko 2018-03-01 22:29:18 -05:00 committed by Lioncash
parent a6981c9b91
commit 59ec6876bd
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1 changed files with 11 additions and 0 deletions
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11
qemu/target-sparc/translate.c
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@ -2477,8 +2477,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
case GET_ASI_EXCP:
break;
case GET_ASI_DTWINX: /* Reserved for stda. */
#ifndef TARGET_SPARC64
gen_exception(dc, TT_ILL_INSN);
break;
#else
if (!(dc->def->features & CPU_FEATURE_HYPV)) {
/* Pre OpenSPARC CPUs don't have these */
gen_exception(dc, TT_ILL_INSN);
return;
}
/* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
* are ST_BLKINIT_ ASIs */
/* fall through */
#endif
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(dc->uc, src, addr, da.mem_idx, da.memop);