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target/arm: Convert SETEND
Backports commit 48c04a5dfaf2c08e00b659a22c502ec098999cf1 from qemu
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55390520d6
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5a23a1f020
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@ -24,6 +24,7 @@
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&empty !extern
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&empty !extern
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&i !extern imm
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&i !extern imm
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&setend E
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# Branch with Link and Exchange
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# Branch with Link and Exchange
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@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ----
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DMB 1111 0101 0111 1111 1111 0000 0101 ----
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DMB 1111 0101 0111 1111 1111 0000 0101 ----
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ISB 1111 0101 0111 1111 1111 0000 0110 ----
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ISB 1111 0101 0111 1111 1111 0000 0110 ----
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SB 1111 0101 0111 1111 1111 0000 0111 0000
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SB 1111 0101 0111 1111 1111 0000 0111 0000
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# Set Endianness
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SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend
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@ -10579,6 +10579,19 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
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return true;
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return true;
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}
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}
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static bool trans_SETEND(DisasContext *s, arg_SETEND *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (!ENABLE_ARCH_6) {
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return false;
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}
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if (a->E != (s->be_data == MO_BE)) {
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gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env);
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s->base.is_jmp = DISAS_UPDATE;
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}
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return true;
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}
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/*
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/*
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* Legacy decoder.
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* Legacy decoder.
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*/
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*/
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@ -10673,15 +10686,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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return; /* v7MP: Unallocated memory hint: must NOP */
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return; /* v7MP: Unallocated memory hint: must NOP */
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}
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}
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if ((insn & 0x0ffffdff) == 0x01010000) {
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if ((insn & 0x0e000f00) == 0x0c000100) {
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ARCH(6);
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/* setend */
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if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
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gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env);
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s->base.is_jmp = DISAS_UPDATE;
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}
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return;
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} else if ((insn & 0x0e000f00) == 0x0c000100) {
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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/* iWMMXt register transfer. */
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/* iWMMXt register transfer. */
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if (extract32(s->c15_cpar, 1, 1)) {
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if (extract32(s->c15_cpar, 1, 1)) {
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