yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-23 02:55:06 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Define R5900 MMI class, and LQ and SQ opcode constants

Browse source 
Define MMI class, LQ, and SQ R5900 opdoces.

Backports commit f99c0d6da3424dd48ad1f0345464f63515949be6 from qemu
This commit is contained in:
Fredrik Noring 2018-11-10 11:32:23 -05:00 committed by Lioncash
parent fa90149289
commit 5a6b86a346
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 40 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
qemu/target/mips/translate.c
View file

@ -2082,8 +2082,48 @@ enum {
* MTSAB rs, immediate Move Byte Count to Shift Amount Register
* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
* PROT3W rd, rt Parallel Rotate 3 Words
*
* The TX79-specific Multimedia Instruction encodings
* ==================================================
*
* TX79 Multimedia Instruction encoding table keys:
*
* * This code is reserved for future use. An attempt to execute it
* causes a Reserved Instruction exception.
* % This code indicates an instruction class. The instruction word
* must be further decoded by examining additional tables that show
* the values for other instruction fields.
* # This code is reserved for the unsupported instructions DMULT,
* DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
* to execute it causes a Reserved Instruction exception.
*
* TX79 Multimedia Instructions encoded by opcode field (MMI, LQ, SQ):
*
* 31 26 0
* +--------+----------------------------------------+
* | opcode | |
* +--------+----------------------------------------+
*
* opcode bits 28..26
* bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
* 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
* -------+-------+-------+-------+-------+-------+-------+-------+-------
* 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
* 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
* 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
* 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
* 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
* 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
* 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
* 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
*/
enum {
TX79_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
TX79_LQ = 0x1E << 26, /* Same as OPC_MSA */
TX79_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
#define gen_helper_0e0i(tcg_ctx, name, arg) do { \
TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg); \
gen_helper_##name(tcg_ctx, tcg_ctx->cpu_env, helper_tmp); \