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target-arm: Fix AArch32:AArch64 general-purpose register mapping

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There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and
AArch64. This commit fixes the mapping to match the v8 ARM ARM
section D1.20.1 (table D1-77).

Backports commit 3a9148d0bdcee990fbe86759b9b1f5723c1d7fbc from qemu
This commit is contained in:
Sergey Sorokin 2018-02-15 11:02:04 -05:00 committed by Lioncash
parent 83aa10f77d
commit 5b40cb8562
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 32 additions and 32 deletions
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64
qemu/target-arm/helper.c
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@ -4705,35 +4705,35 @@ void aarch64_sync_32_to_64(CPUARMState *env)
}
if (mode == ARM_CPU_MODE_IRQ) {
env->xregs[16] = env->regs[13];
env->xregs[17] = env->regs[14];
env->xregs[16] = env->regs[14];
env->xregs[17] = env->regs[13];
} else {
env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
}
if (mode == ARM_CPU_MODE_SVC) {
env->xregs[18] = env->regs[13];
env->xregs[19] = env->regs[14];
env->xregs[18] = env->regs[14];
env->xregs[19] = env->regs[13];
} else {
env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
}
if (mode == ARM_CPU_MODE_ABT) {
env->xregs[20] = env->regs[13];
env->xregs[21] = env->regs[14];
env->xregs[20] = env->regs[14];
env->xregs[21] = env->regs[13];
} else {
env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
}
if (mode == ARM_CPU_MODE_UND) {
env->xregs[22] = env->regs[13];
env->xregs[23] = env->regs[14];
env->xregs[22] = env->regs[14];
env->xregs[23] = env->regs[13];
} else {
env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
@ -4810,35 +4810,35 @@ void aarch64_sync_64_to_32(CPUARMState *env)
}
if (mode == ARM_CPU_MODE_IRQ) {
env->regs[13] = env->xregs[16];
env->regs[14] = env->xregs[17];
env->regs[14] = env->xregs[16];
env->regs[13] = env->xregs[17];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
}
if (mode == ARM_CPU_MODE_SVC) {
env->regs[13] = env->xregs[18];
env->regs[14] = env->xregs[19];
env->regs[14] = env->xregs[18];
env->regs[13] = env->xregs[19];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
}
if (mode == ARM_CPU_MODE_ABT) {
env->regs[13] = env->xregs[20];
env->regs[14] = env->xregs[21];
env->regs[14] = env->xregs[20];
env->regs[13] = env->xregs[21];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
}
if (mode == ARM_CPU_MODE_UND) {
env->regs[13] = env->xregs[22];
env->regs[14] = env->xregs[23];
env->regs[14] = env->xregs[22];
env->regs[13] = env->xregs[23];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ