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RISC-V: Add support for the Zifencei extension
fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu
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e006204543
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5b59f956b3
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@ -221,6 +221,10 @@ typedef struct RISCVCPU {
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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struct {
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bool ext_ifencei;
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} cfg;
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} RISCVCPU;
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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@ -502,6 +502,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
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static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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{
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if (!ctx->ext_ifencei) {
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return false;
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}
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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/*
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@ -52,6 +52,7 @@ typedef struct DisasContext {
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to any system register, which includes CSR_FRM, so we do not have
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to reset this known value. */
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int frm;
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bool ext_ifencei;
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// Unicorn engine
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struct uc_struct *uc;
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@ -781,6 +782,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cs->env_ptr;
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RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
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ctx->uc = cs->uc;
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ctx->pc_succ_insn = ctx->base.pc_first;
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@ -789,6 +791,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->priv_ver = env->priv_ver;
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ctx->misa = env->misa;
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ctx->frm = -1; /* unknown rounding mode */
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ctx->ext_ifencei = cpu->cfg.ext_ifencei;
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}
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static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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