RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.

Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu

qemu/target/riscv/cpu.h

@@ -221,6 +221,10 @@ typedef struct RISCVCPU {
     /*< public >*/
     CPUNegativeOffsetState neg;
     CPURISCVState env;
+
+    struct {
+        bool ext_ifencei;
+    } cfg;
 } RISCVCPU;
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)

qemu/target/riscv/insn_trans/trans_rvi.inc.c

@@ -502,6 +502,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
 
 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 {
+    if (!ctx->ext_ifencei) {
+        return false;
+    }
+
     TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
 
     /*

qemu/target/riscv/translate.c

@@ -52,6 +52,7 @@ typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
+    bool ext_ifencei;
 
     // Unicorn engine
     struct uc_struct *uc;
@@ -781,6 +782,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPURISCVState *env = cs->env_ptr;
+    RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
 
     ctx->uc = cs->uc;
     ctx->pc_succ_insn = ctx->base.pc_first;
@@ -789,6 +791,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->priv_ver = env->priv_ver;
     ctx->misa = env->misa;
     ctx->frm = -1;  /* unknown rounding mode */
+    ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)