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target/arm: Split out gen_gvec_ool_zzz

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Backports e645d1a17a359156c6047006d760ca176d493edb
This commit is contained in:
Richard Henderson 2021-02-26 14:29:46 -05:00 committed by Lioncash
parent aa3819c396
commit 5bd98feed9
1 changed files with 19 additions and 42 deletions
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61
qemu/target/arm/translate-sve.c
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@ -139,6 +139,18 @@ static int pred_gvec_reg_size(DisasContext *s)
return size_for_gvec(pred_full_reg_size(s));
}
/* Invoke an out-of-line helper on 3 Zregs. */
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
int rd, int rn, int rm, int data)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
vsz, vsz, data, fn);
}
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
int rd, int rn, int pg, int data)
@ -779,12 +791,7 @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
return false;
}
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, 0, fn);
gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
}
return true;
}
@ -813,12 +820,7 @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
};
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, 0, fns[a->u][a->sz]);
gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
}
return true;
}
@ -831,12 +833,7 @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
};
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, a->index, fns[a->u][a->sz]);
gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
}
return true;
}
@ -1002,12 +999,7 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
{
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, a->imm, fn);
gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
}
return true;
}
@ -1069,12 +1061,7 @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
return false;
}
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, 0, fns[a->esz]);
gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
}
return true;
}
@ -2150,12 +2137,7 @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
};
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, 0, fns[a->esz]);
gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
}
return true;
}
@ -2332,12 +2314,7 @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
gen_helper_gvec_3 *fn)
{
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, data, fn);
gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
}
return true;
}