yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 14:15:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

riscv: Add helper to make NaN-boxing for FP register

Browse source 
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.

Backports commit 354908cee1f7ff761b5fedbdb6376c378c10f941 from qemu
This commit is contained in:
Ian Jiang 2021-02-25 11:53:14 -05:00 committed by Lioncash
parent e5725839b9
commit 5c3a2f391c
2 changed files with 19 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/riscv/cpu.h
View file

@ -37,7 +37,9 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")

19
qemu/target/riscv/insn_trans/trans_rvf.inc.c
View file

@ -23,6 +23,22 @@
return false; \
} while (0)
/*
* RISC-V requires NaN-boxing of narrower width floating
* point values. This applies when a 32-bit value is
* assigned to a 64-bit FP register. Thus this does not
* apply when the RVD extension is not present.
*/
static void gen_nanbox_fpr(DisasContext *ctx, int regno)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
if (has_ext(ctx, RVD)) {
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[regno], tcg_ctx->cpu_fpr_risc[regno],
MAKE_64BIT_MASK(32, 32));
}
}
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
@ -33,8 +49,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(tcg_ctx, tcg_ctx->cpu_fpr_risc[a->rd], tcg_ctx->cpu_fpr_risc[a->rd], 0xffffffff00000000ULL);
gen_nanbox_fpr(ctx, a->rd);
tcg_temp_free(tcg_ctx, t0);
mark_fs_dirty(ctx);