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target-hppa: Add softfloat specializations

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Like the original MIPS, HPPA has the MSB of an SNaN set.
However, it has different rules for silencing an SNaN:
(1) msb is cleared and (2) msb-1 must be set if the fraction
is now zero, and (implementation defined) may be set always.
I haven't checked real hardware but chose the set always
alternative because it's easy and within spec.

Backports commit 005fa38d86257d471ac461c066a5409a9f5ebb02 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 23:42:01 -05:00 committed by Lioncash
parent 11c66029b7
commit 5c4f79ac62
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 19 additions and 1 deletions
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20
qemu/fpu/softfloat-specialize.h
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@ -116,6 +116,8 @@ float32 float32_default_nan(float_status *status)
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_XTENSA) defined(TARGET_XTENSA)
return const_float32(0x7FC00000); return const_float32(0x7FC00000);
#elif defined(TARGET_HPPA)
return const_float32(0x7FA00000);
#else #else
if (status->snan_bit_is_one) { if (status->snan_bit_is_one) {
return const_float32(0x7FBFFFFF); return const_float32(0x7FBFFFFF);
@ -138,6 +140,8 @@ float64 float64_default_nan(float_status *status)
return const_float64(LIT64(0x7FFFFFFFFFFFFFFF)); return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
return const_float64(LIT64(0x7FF8000000000000)); return const_float64(LIT64(0x7FF8000000000000));
#elif defined(TARGET_HPPA)
return const_float64(LIT64(0x7FF4000000000000));
#else #else
if (status->snan_bit_is_one) { if (status->snan_bit_is_one) {
return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
@ -361,7 +365,14 @@ float32 float32_maybe_silence_nan(float32 a_, float_status *status)
{ {
if (float32_is_signaling_nan(a_, status)) { if (float32_is_signaling_nan(a_, status)) {
if (status->snan_bit_is_one) { if (status->snan_bit_is_one) {
#ifdef TARGET_HPPA
uint32_t a = float32_val(a_);
a &= ~0x00400000;
a |= 0x00200000;
return make_float32(a);
#else
return float32_default_nan(status); return float32_default_nan(status);
#endif
} else { } else {
uint32_t a = float32_val(a_); uint32_t a = float32_val(a_);
a |= (1 << 22); a |= (1 << 22);
@ -449,7 +460,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return 1; return 1;
} }
} }
#elif defined(TARGET_MIPS) #elif defined(TARGET_MIPS) || defined(TARGET_HPPA)
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand) flag aIsLargerSignificand)
{ {
@ -789,7 +800,14 @@ float64 float64_maybe_silence_nan(float64 a_, float_status *status)
{ {
if (float64_is_signaling_nan(a_, status)) { if (float64_is_signaling_nan(a_, status)) {
if (status->snan_bit_is_one) { if (status->snan_bit_is_one) {
#ifdef TARGET_HPPA
uint64_t a = float64_val(a_);
a &= ~0x0008000000000000ULL;
a |= 0x0004000000000000ULL;
return make_float64(a);
#else
return float64_default_nan(status); return float64_default_nan(status);
#endif
} else { } else {
uint64_t a = float64_val(a_); uint64_t a = float64_val(a_);
a |= LIT64(0x0008000000000000); a |= LIT64(0x0008000000000000);