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target-arm: Implement YIELD insn to yield in ARM and Thumb translators

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Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)

Backports commit c87e5a61c2b3024116f52f7e68273f864ff7ab82 from qemu
This commit is contained in:
Peter Maydell 2018-02-14 02:05:44 -05:00 committed by Lioncash
parent 8840d8370d
commit 5c7389680e
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 0 deletions
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7
qemu/target-arm/translate.c
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@ -4221,6 +4221,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
static void gen_nop_hint(DisasContext *s, int val) static void gen_nop_hint(DisasContext *s, int val)
{ {
switch (val) { switch (val) {
case 1: /* yield */
gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_YIELD;
break;
case 3: /* wfi */ case 3: /* wfi */
gen_set_pc_im(s, s->pc); gen_set_pc_im(s, s->pc);
s->is_jmp = DISAS_WFI; s->is_jmp = DISAS_WFI;
@ -11699,6 +11703,9 @@ tb_end:
case DISAS_WFE: case DISAS_WFE:
gen_helper_wfe(tcg_ctx, tcg_ctx->cpu_env); gen_helper_wfe(tcg_ctx, tcg_ctx->cpu_env);
break; break;
case DISAS_YIELD:
gen_helper_yield(tcg_ctx, tcg_ctx->cpu_env);
break;
case DISAS_SWI: case DISAS_SWI:
gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
default_exception_el(dc)); default_exception_el(dc));