mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-02-25 18:56:44 +00:00
target/arm: Add isar_feature tests for PAN + ATS1E1
Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Backports commit 3d6ad6bb466f487bcc861f99e2c9054230df1076 from qemu
This commit is contained in:
parent
7aaf0d442b
commit
5c8c2ca505
|
@ -1612,6 +1612,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
|
||||||
FIELD(ID_ISAR6, SB, 12, 4)
|
FIELD(ID_ISAR6, SB, 12, 4)
|
||||||
FIELD(ID_ISAR6, SPECRES, 16, 4)
|
FIELD(ID_ISAR6, SPECRES, 16, 4)
|
||||||
|
|
||||||
|
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
|
||||||
|
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
|
||||||
|
FIELD(ID_MMFR3, BPMAINT, 8, 4)
|
||||||
|
FIELD(ID_MMFR3, MAINTBCST, 12, 4)
|
||||||
|
FIELD(ID_MMFR3, PAN, 16, 4)
|
||||||
|
FIELD(ID_MMFR3, COHWALK, 20, 4)
|
||||||
|
FIELD(ID_MMFR3, CMEMSZ, 24, 4)
|
||||||
|
FIELD(ID_MMFR3, SUPERSEC, 28, 4)
|
||||||
|
|
||||||
FIELD(ID_MMFR4, SPECSEI, 0, 4)
|
FIELD(ID_MMFR4, SPECSEI, 0, 4)
|
||||||
FIELD(ID_MMFR4, AC2, 4, 4)
|
FIELD(ID_MMFR4, AC2, 4, 4)
|
||||||
FIELD(ID_MMFR4, XNX, 8, 4)
|
FIELD(ID_MMFR4, XNX, 8, 4)
|
||||||
|
@ -3316,6 +3325,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
|
||||||
return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
|
return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
|
||||||
|
{
|
||||||
|
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
|
||||||
|
{
|
||||||
|
return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 64-bit feature tests via id registers.
|
* 64-bit feature tests via id registers.
|
||||||
*/
|
*/
|
||||||
|
@ -3475,6 +3494,16 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
|
||||||
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
|
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
|
||||||
|
{
|
||||||
|
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
|
||||||
|
{
|
||||||
|
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
|
||||||
|
}
|
||||||
|
|
||||||
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
|
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
|
||||||
{
|
{
|
||||||
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
|
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
|
||||||
|
|
Loading…
Reference in a new issue