target/arm: Split helper_crypto_sha1_3reg

Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Backports commit afc8b7d32668547308bdd654a63cf5228936e0ba from qemu

qemu/aarch64.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_aarch64
 #define helper_crypto_aesmc helper_crypto_aesmc_aarch64
 #define helper_crypto_rax1 helper_crypto_rax1_aarch64
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_aarch64
+#define helper_crypto_sha1c helper_crypto_sha1c_aarch64
 #define helper_crypto_sha1h helper_crypto_sha1h_aarch64
+#define helper_crypto_sha1m helper_crypto_sha1m_aarch64
+#define helper_crypto_sha1p helper_crypto_sha1p_aarch64
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_aarch64
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_aarch64
 #define helper_crypto_sha256h helper_crypto_sha256h_aarch64
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_aarch64

qemu/aarch64eb.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_aarch64eb
 #define helper_crypto_aesmc helper_crypto_aesmc_aarch64eb
 #define helper_crypto_rax1 helper_crypto_rax1_aarch64eb
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_aarch64eb
+#define helper_crypto_sha1c helper_crypto_sha1c_aarch64eb
 #define helper_crypto_sha1h helper_crypto_sha1h_aarch64eb
+#define helper_crypto_sha1m helper_crypto_sha1m_aarch64eb
+#define helper_crypto_sha1p helper_crypto_sha1p_aarch64eb
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_aarch64eb
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_aarch64eb
 #define helper_crypto_sha256h helper_crypto_sha256h_aarch64eb
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_aarch64eb

qemu/arm.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_arm
 #define helper_crypto_aesmc helper_crypto_aesmc_arm
 #define helper_crypto_rax1 helper_crypto_rax1_arm
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_arm
+#define helper_crypto_sha1c helper_crypto_sha1c_arm
 #define helper_crypto_sha1h helper_crypto_sha1h_arm
+#define helper_crypto_sha1m helper_crypto_sha1m_arm
+#define helper_crypto_sha1p helper_crypto_sha1p_arm
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_arm
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_arm
 #define helper_crypto_sha256h helper_crypto_sha256h_arm
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_arm

qemu/armeb.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_armeb
 #define helper_crypto_aesmc helper_crypto_aesmc_armeb
 #define helper_crypto_rax1 helper_crypto_rax1_armeb
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_armeb
+#define helper_crypto_sha1c helper_crypto_sha1c_armeb
 #define helper_crypto_sha1h helper_crypto_sha1h_armeb
+#define helper_crypto_sha1m helper_crypto_sha1m_armeb
+#define helper_crypto_sha1p helper_crypto_sha1p_armeb
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_armeb
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_armeb
 #define helper_crypto_sha256h helper_crypto_sha256h_armeb
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_armeb

qemu/header_gen.py

@@ -1085,8 +1085,11 @@ symbols = (
     'helper_crypto_aese',
     'helper_crypto_aesmc',
     'helper_crypto_rax1',
-    'helper_crypto_sha1_3reg',
+    'helper_crypto_sha1c',
     'helper_crypto_sha1h',
+    'helper_crypto_sha1m',
+    'helper_crypto_sha1p',
+    'helper_crypto_sha1su0',
     'helper_crypto_sha1su1',
     'helper_crypto_sha256h',
     'helper_crypto_sha256h2',

qemu/m68k.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_m68k
 #define helper_crypto_aesmc helper_crypto_aesmc_m68k
 #define helper_crypto_rax1 helper_crypto_rax1_m68k
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_m68k
+#define helper_crypto_sha1c helper_crypto_sha1c_m68k
 #define helper_crypto_sha1h helper_crypto_sha1h_m68k
+#define helper_crypto_sha1m helper_crypto_sha1m_m68k
+#define helper_crypto_sha1p helper_crypto_sha1p_m68k
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_m68k
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_m68k
 #define helper_crypto_sha256h helper_crypto_sha256h_m68k
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_m68k

qemu/mips.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_mips
 #define helper_crypto_aesmc helper_crypto_aesmc_mips
 #define helper_crypto_rax1 helper_crypto_rax1_mips
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_mips
+#define helper_crypto_sha1c helper_crypto_sha1c_mips
 #define helper_crypto_sha1h helper_crypto_sha1h_mips
+#define helper_crypto_sha1m helper_crypto_sha1m_mips
+#define helper_crypto_sha1p helper_crypto_sha1p_mips
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_mips
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_mips
 #define helper_crypto_sha256h helper_crypto_sha256h_mips
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_mips

qemu/mips64.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_mips64
 #define helper_crypto_aesmc helper_crypto_aesmc_mips64
 #define helper_crypto_rax1 helper_crypto_rax1_mips64
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_mips64
+#define helper_crypto_sha1c helper_crypto_sha1c_mips64
 #define helper_crypto_sha1h helper_crypto_sha1h_mips64
+#define helper_crypto_sha1m helper_crypto_sha1m_mips64
+#define helper_crypto_sha1p helper_crypto_sha1p_mips64
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_mips64
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_mips64
 #define helper_crypto_sha256h helper_crypto_sha256h_mips64
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_mips64

qemu/mips64el.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_mips64el
 #define helper_crypto_aesmc helper_crypto_aesmc_mips64el
 #define helper_crypto_rax1 helper_crypto_rax1_mips64el
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_mips64el
+#define helper_crypto_sha1c helper_crypto_sha1c_mips64el
 #define helper_crypto_sha1h helper_crypto_sha1h_mips64el
+#define helper_crypto_sha1m helper_crypto_sha1m_mips64el
+#define helper_crypto_sha1p helper_crypto_sha1p_mips64el
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_mips64el
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_mips64el
 #define helper_crypto_sha256h helper_crypto_sha256h_mips64el
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_mips64el

qemu/mipsel.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_mipsel
 #define helper_crypto_aesmc helper_crypto_aesmc_mipsel
 #define helper_crypto_rax1 helper_crypto_rax1_mipsel
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_mipsel
+#define helper_crypto_sha1c helper_crypto_sha1c_mipsel
 #define helper_crypto_sha1h helper_crypto_sha1h_mipsel
+#define helper_crypto_sha1m helper_crypto_sha1m_mipsel
+#define helper_crypto_sha1p helper_crypto_sha1p_mipsel
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_mipsel
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_mipsel
 #define helper_crypto_sha256h helper_crypto_sha256h_mipsel
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_mipsel

qemu/powerpc.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_powerpc
 #define helper_crypto_aesmc helper_crypto_aesmc_powerpc
 #define helper_crypto_rax1 helper_crypto_rax1_powerpc
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_powerpc
+#define helper_crypto_sha1c helper_crypto_sha1c_powerpc
 #define helper_crypto_sha1h helper_crypto_sha1h_powerpc
+#define helper_crypto_sha1m helper_crypto_sha1m_powerpc
+#define helper_crypto_sha1p helper_crypto_sha1p_powerpc
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_powerpc
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_powerpc
 #define helper_crypto_sha256h helper_crypto_sha256h_powerpc
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_powerpc

qemu/riscv32.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_riscv32
 #define helper_crypto_aesmc helper_crypto_aesmc_riscv32
 #define helper_crypto_rax1 helper_crypto_rax1_riscv32
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_riscv32
+#define helper_crypto_sha1c helper_crypto_sha1c_riscv32
 #define helper_crypto_sha1h helper_crypto_sha1h_riscv32
+#define helper_crypto_sha1m helper_crypto_sha1m_riscv32
+#define helper_crypto_sha1p helper_crypto_sha1p_riscv32
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_riscv32
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_riscv32
 #define helper_crypto_sha256h helper_crypto_sha256h_riscv32
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_riscv32

qemu/riscv64.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_riscv64
 #define helper_crypto_aesmc helper_crypto_aesmc_riscv64
 #define helper_crypto_rax1 helper_crypto_rax1_riscv64
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_riscv64
+#define helper_crypto_sha1c helper_crypto_sha1c_riscv64
 #define helper_crypto_sha1h helper_crypto_sha1h_riscv64
+#define helper_crypto_sha1m helper_crypto_sha1m_riscv64
+#define helper_crypto_sha1p helper_crypto_sha1p_riscv64
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_riscv64
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_riscv64
 #define helper_crypto_sha256h helper_crypto_sha256h_riscv64
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_riscv64

qemu/sparc.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_sparc
 #define helper_crypto_aesmc helper_crypto_aesmc_sparc
 #define helper_crypto_rax1 helper_crypto_rax1_sparc
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_sparc
+#define helper_crypto_sha1c helper_crypto_sha1c_sparc
 #define helper_crypto_sha1h helper_crypto_sha1h_sparc
+#define helper_crypto_sha1m helper_crypto_sha1m_sparc
+#define helper_crypto_sha1p helper_crypto_sha1p_sparc
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_sparc
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_sparc
 #define helper_crypto_sha256h helper_crypto_sha256h_sparc
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_sparc

qemu/sparc64.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_sparc64
 #define helper_crypto_aesmc helper_crypto_aesmc_sparc64
 #define helper_crypto_rax1 helper_crypto_rax1_sparc64
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_sparc64
+#define helper_crypto_sha1c helper_crypto_sha1c_sparc64
 #define helper_crypto_sha1h helper_crypto_sha1h_sparc64
+#define helper_crypto_sha1m helper_crypto_sha1m_sparc64
+#define helper_crypto_sha1p helper_crypto_sha1p_sparc64
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_sparc64
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_sparc64
 #define helper_crypto_sha256h helper_crypto_sha256h_sparc64
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_sparc64

qemu/target/arm/crypto_helper.c

@@ -25,11 +25,11 @@ union CRYPTO_STATE {
 };
 
 #ifdef HOST_WORDS_BIGENDIAN
-#define CR_ST_BYTE(state, i)   (state.bytes[(15 - (i)) ^ 8])
+#define CR_ST_BYTE(state, i)   ((state).bytes[(15 - (i)) ^ 8])
-#define CR_ST_WORD(state, i)   (state.words[(3 - (i)) ^ 2])
+#define CR_ST_WORD(state, i)   ((state).words[(3 - (i)) ^ 2])
 #else
-#define CR_ST_BYTE(state, i)   (state.bytes[i])
+#define CR_ST_BYTE(state, i)   ((state).bytes[i])
-#define CR_ST_WORD(state, i)   (state.words[i])
+#define CR_ST_WORD(state, i)   ((state).words[i])
 #endif
 
 /*
@@ -259,55 +259,73 @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
     return (x & y) | ((x | y) & z);
 }
 
-void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op)
+void HELPER(crypto_sha1su0)(void *vd, void *vn, void *vm, uint32_t desc)
 {
-    uint64_t *rd = vd;
+    uint64_t *d = vd, *n = vn, *m = vm;
-    uint64_t *rn = vn;
+    uint64_t d0, d1;
-    uint64_t *rm = vm;
-    union CRYPTO_STATE d;
-    union CRYPTO_STATE n;
-    union CRYPTO_STATE m;
-    d.l[0] = rd[0];
-    d.l[1] = rd[1];
-    n.l[0] = rn[0];
-    n.l[1] = rn[1];
-    m.l[0] = rm[0];
-    m.l[1] = rm[1];
 
-    if (op == 3) { /* sha1su0 */
+    d0 = d[1] ^ d[0] ^ m[0];
-        d.l[0] ^= d.l[1] ^ m.l[0];
+    d1 = n[0] ^ d[1] ^ m[1];
-        d.l[1] ^= n.l[0] ^ m.l[1];
+    d[0] = d0;
-    } else {
+    d[1] = d1;
-        int i;
 
-        for (i = 0; i < 4; i++) {
+    clear_tail_16(vd, desc);
-            uint32_t t;
+}
 
-            switch (op) {
+static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn,
-            case 0: /* sha1c */
+                                    uint64_t *rm, uint32_t desc,
-                t = cho(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
+                                    uint32_t (*fn)(union CRYPTO_STATE *d))
-                break;
+{
-            case 1: /* sha1p */
+    union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };
-                t = par(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
+    union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };
-                break;
+    union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };
-            case 2: /* sha1m */
+    int i;
-                t = maj(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3));
-                break;
-            default:
-                g_assert_not_reached();
-            }
-            t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
-                 + CR_ST_WORD(m, i);
 
-            CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
+    for (i = 0; i < 4; i++) {
-            CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
+        uint32_t t = fn(&d);
-            CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
+
-            CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
+        t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0)
-            CR_ST_WORD(d, 0) = t;
+             + CR_ST_WORD(m, i);
-        }
+
+        CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3);
+        CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2);
+        CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2);
+        CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0);
+        CR_ST_WORD(d, 0) = t;
     }
     rd[0] = d.l[0];
     rd[1] = d.l[1];
+    clear_tail_16(rd, desc);
+}
+
+static uint32_t do_sha1c(union CRYPTO_STATE *d)
+{
+    return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
+}
+
+void HELPER(crypto_sha1c)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1c);
+}
+
+static uint32_t do_sha1p(union CRYPTO_STATE *d)
+{
+    return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
+}
+
+void HELPER(crypto_sha1p)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1p);
+}
+
+static uint32_t do_sha1m(union CRYPTO_STATE *d)
+{
+    return maj(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3));
+}
+
+void HELPER(crypto_sha1m)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    crypto_sha1_3reg(vd, vn, vm, desc, do_sha1m);
 }
 
 void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc)

qemu/target/arm/helper.h

@@ -509,7 +509,10 @@ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr)
 DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
-DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 

qemu/target/arm/neon-dp.decode

@@ -168,8 +168,10 @@ VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
 @3same_crypto    .... .... .... .... .... .... .... .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
 
-SHA1_3s          1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
+SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
-                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
+SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
+SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
 SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
 SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
 SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto

qemu/target/arm/translate-a64.c

@@ -13763,7 +13763,6 @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
  */
 static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
     int size = extract32(insn, 22, 2);
     int opcode = extract32(insn, 12, 3);
     int rm = extract32(insn, 16, 5);
@@ -13779,10 +13778,19 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
 
     switch (opcode) {
     case 0: /* SHA1C */
+        genfn = gen_helper_crypto_sha1c;
+        feature = dc_isar_feature(aa64_sha1, s);
+        break;
     case 1: /* SHA1P */
+        genfn = gen_helper_crypto_sha1p;
+        feature = dc_isar_feature(aa64_sha1, s);
+        break;
     case 2: /* SHA1M */
+        genfn = gen_helper_crypto_sha1m;
+        feature = dc_isar_feature(aa64_sha1, s);
+        break;
     case 3: /* SHA1SU0 */
-        genfn = NULL;
+        genfn = gen_helper_crypto_sha1su0;
         feature = dc_isar_feature(aa64_sha1, s);
         break;
     case 4: /* SHA256H */
@@ -13811,22 +13819,7 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
         return;
     }
 
-    if (genfn) {
+    gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
-        gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn);
-    } else {
-        TCGv_i32 tcg_opcode = tcg_const_i32(tcg_ctx, opcode);
-        TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd);
-        TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn);
-        TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm);
-
-        gen_helper_crypto_sha1_3reg(tcg_ctx, tcg_rd_ptr, tcg_rn_ptr,
-                                    tcg_rm_ptr, tcg_opcode);
-
-        tcg_temp_free_i32(tcg_ctx, tcg_opcode);
-        tcg_temp_free_ptr(tcg_ctx, tcg_rd_ptr);
-        tcg_temp_free_ptr(tcg_ctx, tcg_rn_ptr);
-        tcg_temp_free_ptr(tcg_ctx, tcg_rm_ptr);
-    }
 }
 
 /* Crypto two-reg SHA

qemu/target/arm/translate-neon.inc.c

@@ -706,43 +706,20 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
 DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
 DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
 
-static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
+#define DO_SHA1(NAME, FUNC)                                             \
-{
+    WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \
-    TCGv_ptr ptr1, ptr2, ptr3;
+    static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a)        \
-    TCGv_i32 tmp;
+    {                                                                   \
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+        if (!dc_isar_feature(aa32_sha1, s)) {                           \
-
+            return false;                                               \
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
+        }                                                               \
-        !dc_isar_feature(aa32_sha1, s)) {
+        return do_3same(s, a, gen_##NAME##_3s);                         \
-        return false;
     }
 
-    /* UNDEF accesses to D16-D31 if they don't exist. */
+DO_SHA1(SHA1C, gen_helper_crypto_sha1c)
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
+DO_SHA1(SHA1P, gen_helper_crypto_sha1p)
-        ((a->vd | a->vn | a->vm) & 0x10)) {
+DO_SHA1(SHA1M, gen_helper_crypto_sha1m)
-        return false;
+DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0)
-    }
-
-    if ((a->vn | a->vm | a->vd) & 1) {
-        return false;
-    }
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    ptr1 = vfp_reg_ptr(s, true, a->vd);
-    ptr2 = vfp_reg_ptr(s, true, a->vn);
-    ptr3 = vfp_reg_ptr(s, true, a->vm);
-    tmp = tcg_const_i32(tcg_ctx, a->optype);
-    gen_helper_crypto_sha1_3reg(tcg_ctx, ptr1, ptr2, ptr3, tmp);
-    tcg_temp_free_i32(tcg_ctx, tmp);
-    tcg_temp_free_ptr(tcg_ctx, ptr1);
-    tcg_temp_free_ptr(tcg_ctx, ptr2);
-    tcg_temp_free_ptr(tcg_ctx, ptr3);
-
-    return true;
-}
 
 #define DO_SHA2(NAME, FUNC)                                             \
     WRAP_OOL_FN(gen_##NAME##_3s, FUNC)                                  \

qemu/x86_64.h

@@ -1079,8 +1079,11 @@
 #define helper_crypto_aese helper_crypto_aese_x86_64
 #define helper_crypto_aesmc helper_crypto_aesmc_x86_64
 #define helper_crypto_rax1 helper_crypto_rax1_x86_64
-#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_x86_64
+#define helper_crypto_sha1c helper_crypto_sha1c_x86_64
 #define helper_crypto_sha1h helper_crypto_sha1h_x86_64
+#define helper_crypto_sha1m helper_crypto_sha1m_x86_64
+#define helper_crypto_sha1p helper_crypto_sha1p_x86_64
+#define helper_crypto_sha1su0 helper_crypto_sha1su0_x86_64
 #define helper_crypto_sha1su1 helper_crypto_sha1su1_x86_64
 #define helper_crypto_sha256h helper_crypto_sha256h_x86_64
 #define helper_crypto_sha256h2 helper_crypto_sha256h2_x86_64