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target-mips: signal RI for removed instructions in microMIPS R6

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Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.

Backports commit 9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da from qemu
This commit is contained in:
Yongbok Kim 2018-02-13 21:40:22 -05:00 committed by Lioncash
parent acede6f50c
commit 5cca75ca10
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 68 additions and 0 deletions
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68
qemu/target-mips/translate.c
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@ -13358,15 +13358,19 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_bshfl(ctx, OPC_WSBH, rs, rt); gen_bshfl(ctx, OPC_WSBH, rs, rt);
break; break;
case MULT: case MULT:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MULT; mips32_op = OPC_MULT;
goto do_mul; goto do_mul;
case MULTU: case MULTU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MULTU; mips32_op = OPC_MULTU;
goto do_mul; goto do_mul;
case DIV: case DIV:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_DIV; mips32_op = OPC_DIV;
goto do_div; goto do_div;
case DIVU: case DIVU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_DIVU; mips32_op = OPC_DIVU;
goto do_div; goto do_div;
do_div: do_div:
@ -13374,15 +13378,19 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
gen_muldiv(ctx, mips32_op, 0, rs, rt); gen_muldiv(ctx, mips32_op, 0, rs, rt);
break; break;
case MADD: case MADD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MADD; mips32_op = OPC_MADD;
goto do_mul; goto do_mul;
case MADDU: case MADDU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MADDU; mips32_op = OPC_MADDU;
goto do_mul; goto do_mul;
case MSUB: case MSUB:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUB; mips32_op = OPC_MSUB;
goto do_mul; goto do_mul;
case MSUBU: case MSUBU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUBU; mips32_op = OPC_MSUBU;
do_mul: do_mul:
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
@ -13415,6 +13423,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
break; break;
case JALRS: case JALRS:
case JALRS_HB: case JALRS_HB:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break; break;
@ -13543,6 +13552,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
} }
break; break;
case 0x35: case 0x35:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
switch (minor) { switch (minor) {
case MFHI32: case MFHI32:
gen_HILO(ctx, OPC_MFHI, 0, rs); gen_HILO(ctx, OPC_MFHI, 0, rs);
@ -13815,6 +13825,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVT, 5): case COND_FLOAT_MOV(MOVT, 5):
case COND_FLOAT_MOV(MOVT, 6): case COND_FLOAT_MOV(MOVT, 6):
case COND_FLOAT_MOV(MOVT, 7): case COND_FLOAT_MOV(MOVT, 7):
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1);
break; break;
case COND_FLOAT_MOV(MOVF, 0): case COND_FLOAT_MOV(MOVF, 0):
@ -13825,6 +13836,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
case COND_FLOAT_MOV(MOVF, 5): case COND_FLOAT_MOV(MOVF, 5):
case COND_FLOAT_MOV(MOVF, 6): case COND_FLOAT_MOV(MOVF, 6):
case COND_FLOAT_MOV(MOVF, 7): case COND_FLOAT_MOV(MOVF, 7):
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0);
break; break;
default: default:
@ -13895,6 +13907,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SUBU; mips32_op = OPC_SUBU;
goto do_arith; goto do_arith;
case MUL: case MUL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MUL; mips32_op = OPC_MUL;
do_arith: do_arith:
gen_arith(ctx, mips32_op, rd, rs, rt); gen_arith(ctx, mips32_op, rd, rs, rt);
@ -14026,47 +14039,61 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
switch (minor) { switch (minor) {
case ALNV_PS: case ALNV_PS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_ALNV_PS; mips32_op = OPC_ALNV_PS;
goto do_madd; goto do_madd;
case MADD_S: case MADD_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MADD_S; mips32_op = OPC_MADD_S;
goto do_madd; goto do_madd;
case MADD_D: case MADD_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MADD_D; mips32_op = OPC_MADD_D;
goto do_madd; goto do_madd;
case MADD_PS: case MADD_PS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MADD_PS; mips32_op = OPC_MADD_PS;
goto do_madd; goto do_madd;
case MSUB_S: case MSUB_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUB_S; mips32_op = OPC_MSUB_S;
goto do_madd; goto do_madd;
case MSUB_D: case MSUB_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUB_D; mips32_op = OPC_MSUB_D;
goto do_madd; goto do_madd;
case MSUB_PS: case MSUB_PS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUB_PS; mips32_op = OPC_MSUB_PS;
goto do_madd; goto do_madd;
case NMADD_S: case NMADD_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMADD_S; mips32_op = OPC_NMADD_S;
goto do_madd; goto do_madd;
case NMADD_D: case NMADD_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMADD_D; mips32_op = OPC_NMADD_D;
goto do_madd; goto do_madd;
case NMADD_PS: case NMADD_PS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMADD_PS; mips32_op = OPC_NMADD_PS;
goto do_madd; goto do_madd;
case NMSUB_S: case NMSUB_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMSUB_S; mips32_op = OPC_NMSUB_S;
goto do_madd; goto do_madd;
case NMSUB_D: case NMSUB_D:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMSUB_D; mips32_op = OPC_NMSUB_D;
goto do_madd; goto do_madd;
case NMSUB_PS: case NMSUB_PS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_NMSUB_PS; mips32_op = OPC_NMSUB_PS;
do_madd: do_madd:
gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt);
break; break;
case CABS_COND_FMT: case CABS_COND_FMT:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
cond = (ctx->opcode >> 6) & 0xf; cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7; cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3; fmt = (ctx->opcode >> 10) & 0x3;
@ -14085,6 +14112,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
case C_COND_FMT: case C_COND_FMT:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
cond = (ctx->opcode >> 6) & 0xf; cond = (ctx->opcode >> 6) & 0xf;
cc = (ctx->opcode >> 13) & 0x7; cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 10) & 0x3; fmt = (ctx->opcode >> 10) & 0x3;
@ -14121,6 +14149,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_PUU_PS; mips32_op = OPC_PUU_PS;
goto do_ps; goto do_ps;
case CVT_PS_S: case CVT_PS_S:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_CVT_PS_S; mips32_op = OPC_CVT_PS_S;
do_ps: do_ps:
gen_farith(ctx, mips32_op, rt, rs, rd, 0); gen_farith(ctx, mips32_op, rt, rs, rd, 0);
@ -14133,21 +14162,27 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* [LS][WDU]XC1 */ /* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) { switch ((ctx->opcode >> 6) & 0x7) {
case LWXC1: case LWXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LWXC1; mips32_op = OPC_LWXC1;
goto do_ldst_cp1; goto do_ldst_cp1;
case SWXC1: case SWXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SWXC1; mips32_op = OPC_SWXC1;
goto do_ldst_cp1; goto do_ldst_cp1;
case LDXC1: case LDXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LDXC1; mips32_op = OPC_LDXC1;
goto do_ldst_cp1; goto do_ldst_cp1;
case SDXC1: case SDXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SDXC1; mips32_op = OPC_SDXC1;
goto do_ldst_cp1; goto do_ldst_cp1;
case LUXC1: case LUXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LUXC1; mips32_op = OPC_LUXC1;
goto do_ldst_cp1; goto do_ldst_cp1;
case SUXC1: case SUXC1:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SUXC1; mips32_op = OPC_SUXC1;
do_ldst_cp1: do_ldst_cp1:
gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs);
@ -14158,6 +14193,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break; break;
case 0x18: case 0x18:
/* 3D insns */ /* 3D insns */
check_insn_opc_removed(ctx, ISA_MIPS32R6);
fmt = (ctx->opcode >> 9) & 0x3; fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) { switch ((ctx->opcode >> 6) & 0x7) {
case RSQRT2_FMT: case RSQRT2_FMT:
@ -14240,6 +14276,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
case PREFX: case PREFX:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
break; break;
default: default:
goto pool32f_invalid; goto pool32f_invalid;
@ -14316,31 +14353,39 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
minor = (ctx->opcode >> 21) & 0x1f; minor = (ctx->opcode >> 21) & 0x1f;
switch (minor) { switch (minor) {
case BLTZ: case BLTZ:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4);
break; break;
case BLTZAL: case BLTZAL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break; break;
case BLTZALS: case BLTZALS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break; break;
case BGEZ: case BGEZ:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4);
break; break;
case BGEZAL: case BGEZAL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break; break;
case BGEZALS: case BGEZALS:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
break; break;
case BLEZ: case BLEZ:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4);
break; break;
case BGTZ: case BGTZ:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4);
break; break;
@ -14352,15 +14397,18 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_TGEI; mips32_op = OPC_TGEI;
goto do_trapi; goto do_trapi;
case TLTIU: case TLTIU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TLTIU; mips32_op = OPC_TLTIU;
goto do_trapi; goto do_trapi;
case TGEIU: case TGEIU:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TGEIU; mips32_op = OPC_TGEIU;
goto do_trapi; goto do_trapi;
case TNEI: case TNEI:
mips32_op = OPC_TNEI; mips32_op = OPC_TNEI;
goto do_trapi; goto do_trapi;
case TEQI: case TEQI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TEQI; mips32_op = OPC_TEQI;
do_trapi: do_trapi:
gen_trap(ctx, mips32_op, rs, -1, imm); gen_trap(ctx, mips32_op, rs, -1, imm);
@ -14368,6 +14416,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case BNEZC: case BNEZC:
case BEQZC: case BEQZC:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ, gen_compute_branch(ctx, minor == BNEZC ? OPC_BNE : OPC_BEQ,
4, rs, 0, imm << 1, 0); 4, rs, 0, imm << 1, 0);
/* Compact branches don't have a delay slot, so just let /* Compact branches don't have a delay slot, so just let
@ -14375,28 +14424,35 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
target. */ target. */
break; break;
case LUI: case LUI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
break; break;
case SYNCI: case SYNCI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* Break the TB to be able to sync copied instructions /* Break the TB to be able to sync copied instructions
immediately */ immediately */
ctx->bstate = BS_STOP; ctx->bstate = BS_STOP;
break; break;
case BC2F: case BC2F:
case BC2T: case BC2T:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* COP2: Not implemented. */ /* COP2: Not implemented. */
generate_exception_err(ctx, EXCP_CpU, 2); generate_exception_err(ctx, EXCP_CpU, 2);
break; break;
case BC1F: case BC1F:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F; mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_BC1F;
goto do_cp1branch; goto do_cp1branch;
case BC1T: case BC1T:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T; mips32_op = (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_BC1T;
goto do_cp1branch; goto do_cp1branch;
case BC1ANY4F: case BC1ANY4F:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_BC1FANY4; mips32_op = OPC_BC1FANY4;
goto do_cp1mips3d; goto do_cp1mips3d;
case BC1ANY4T: case BC1ANY4T:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_BC1TANY4; mips32_op = OPC_BC1TANY4;
do_cp1mips3d: do_cp1mips3d:
check_cop1x(ctx); check_cop1x(ctx);
@ -14425,36 +14481,44 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
minor = (ctx->opcode >> 12) & 0xf; minor = (ctx->opcode >> 12) & 0xf;
switch (minor) { switch (minor) {
case LWL: case LWL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LWL; mips32_op = OPC_LWL;
goto do_ld_lr; goto do_ld_lr;
case SWL: case SWL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SWL; mips32_op = OPC_SWL;
goto do_st_lr; goto do_st_lr;
case LWR: case LWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LWR; mips32_op = OPC_LWR;
goto do_ld_lr; goto do_ld_lr;
case SWR: case SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SWR; mips32_op = OPC_SWR;
goto do_st_lr; goto do_st_lr;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case LDL: case LDL:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LDL; mips32_op = OPC_LDL;
goto do_ld_lr; goto do_ld_lr;
case SDL: case SDL:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SDL; mips32_op = OPC_SDL;
goto do_st_lr; goto do_st_lr;
case LDR: case LDR:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_LDR; mips32_op = OPC_LDR;
goto do_ld_lr; goto do_ld_lr;
case SDR: case SDR:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_SDR; mips32_op = OPC_SDR;
goto do_st_lr; goto do_st_lr;
case LWU: case LWU:
@ -14528,6 +14592,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_slt_imm(ctx, mips32_op, rt, rs, imm); gen_slt_imm(ctx, mips32_op, rt, rs, imm);
break; break;
case JALX32: case JALX32:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
@ -14544,10 +14609,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4); gen_compute_branch(ctx, OPC_BNE, 4, rt, rs, imm << 1, 4);
break; break;
case J32: case J32:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_J, 4, rt, rs, gen_compute_branch(ctx, OPC_J, 4, rt, rs,
(int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
break; break;
case JAL32: case JAL32:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch(ctx, OPC_JAL, 4, rt, rs, gen_compute_branch(ctx, OPC_JAL, 4, rt, rs,
(int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4); (int32_t)(ctx->opcode & 0x3FFFFFF) << 1, 4);
ctx->hflags |= MIPS_HFLAG_BDS_STRICT; ctx->hflags |= MIPS_HFLAG_BDS_STRICT;
@ -14736,6 +14803,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *ins
} }
break; break;
case POOL16F: case POOL16F:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->opcode & 1) { if (ctx->opcode & 1) {
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
} else { } else {