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tcg: Implement gvec support for rotate by immediate

Browse source 
No host backend support yet, but the interfaces for rotli
are in place. Canonicalize immediate rotate to the left,
based on a survey of architectures, but provide both left
and right shift interfaces to the translators.

Backports commit b0f7e7444c03da17e41bf327c8aea590104a28ab from qemu
This commit is contained in:
Richard Henderson 2020-06-14 21:25:28 -04:00 committed by Lioncash
parent 50aa85e560
commit 5cce52a04b
28 changed files with 310 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
qemu/aarch64.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64
#define helper_gvec_rotl8i helper_gvec_rotl8i_aarch64
#define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64
#define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64
#define helper_gvec_rotl64i helper_gvec_rotl64i_aarch64
#define helper_gvec_sar8i helper_gvec_sar8i_aarch64
#define helper_gvec_sar8v helper_gvec_sar8v_aarch64
#define helper_gvec_sar16i helper_gvec_sar16i_aarch64
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_aarch64
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_aarch64
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_aarch64
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_aarch64
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_aarch64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_aarch64
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_aarch64
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_aarch64
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_aarch64
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_aarch64

10
qemu/aarch64eb.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64eb
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64eb
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64eb
#define helper_gvec_rotl8i helper_gvec_rotl8i_aarch64eb
#define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64eb
#define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64eb
#define helper_gvec_rotl64i helper_gvec_rotl64i_aarch64eb
#define helper_gvec_sar8i helper_gvec_sar8i_aarch64eb
#define helper_gvec_sar8v helper_gvec_sar8v_aarch64eb
#define helper_gvec_sar16i helper_gvec_sar16i_aarch64eb
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64eb
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_aarch64eb
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64eb
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_aarch64eb
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_aarch64eb
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64eb
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64eb
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64eb
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64eb
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64eb
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64eb
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_aarch64eb
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_aarch64eb
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64eb
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64eb
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64eb
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64eb
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64eb
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64eb
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_aarch64eb
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_aarch64eb
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_aarch64eb
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_aarch64eb
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_aarch64eb

48
qemu/accel/tcg/tcg-runtime-gvec.c
View file

@ -721,6 +721,54 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
clear_high(d, oprsz, desc);
}
void HELPER(gvec_rotl8i)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
int shift = simd_data(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
*(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), shift);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_rotl16i)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
int shift = simd_data(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
*(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), shift);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_rotl32i)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
int shift = simd_data(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
*(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), shift);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_rotl64i)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
int shift = simd_data(desc);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
*(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), shift);
}
clear_high(d, oprsz, desc);
}
void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);

5
qemu/accel/tcg/tcg-runtime.h
View file

@ -259,6 +259,11 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_rotl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_rotl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_rotl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_rotl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

10
qemu/arm.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_arm
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_arm
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_arm
#define helper_gvec_rotl8i helper_gvec_rotl8i_arm
#define helper_gvec_rotl16i helper_gvec_rotl16i_arm
#define helper_gvec_rotl32i helper_gvec_rotl32i_arm
#define helper_gvec_rotl64i helper_gvec_rotl64i_arm
#define helper_gvec_sar8i helper_gvec_sar8i_arm
#define helper_gvec_sar8v helper_gvec_sar8v_arm
#define helper_gvec_sar16i helper_gvec_sar16i_arm
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_arm
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_arm
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_arm
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_arm
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_arm
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_arm
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_arm
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_arm
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_arm
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_arm
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_arm
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_arm
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_arm
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_arm
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_arm
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_arm
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_arm
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_arm
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_arm
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_arm
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_arm
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_arm
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_arm
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_arm

10
qemu/armeb.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_armeb
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_armeb
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_armeb
#define helper_gvec_rotl8i helper_gvec_rotl8i_armeb
#define helper_gvec_rotl16i helper_gvec_rotl16i_armeb
#define helper_gvec_rotl32i helper_gvec_rotl32i_armeb
#define helper_gvec_rotl64i helper_gvec_rotl64i_armeb
#define helper_gvec_sar8i helper_gvec_sar8i_armeb
#define helper_gvec_sar8v helper_gvec_sar8v_armeb
#define helper_gvec_sar16i helper_gvec_sar16i_armeb
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_armeb
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_armeb
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_armeb
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_armeb
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_armeb
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_armeb
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_armeb
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_armeb
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_armeb
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_armeb
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_armeb
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_armeb
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_armeb
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_armeb
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_armeb
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_armeb
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_armeb
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_armeb
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_armeb
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_armeb
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_armeb
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_armeb
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_armeb
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_armeb

10
qemu/header_gen.py
View file

@ -1240,6 +1240,10 @@ symbols = (
'helper_gvec_qrdmlah_s32',
'helper_gvec_qrdmlsh_s16',
'helper_gvec_qrdmlsh_s32',
'helper_gvec_rotl8i',
'helper_gvec_rotl16i',
'helper_gvec_rotl32i',
'helper_gvec_rotl64i',
'helper_gvec_sar8i',
'helper_gvec_sar8v',
'helper_gvec_sar16i',
@ -2910,6 +2914,8 @@ symbols = (
'tcg_gen_gvec_orc',
'tcg_gen_gvec_ori',
'tcg_gen_gvec_ors',
'tcg_gen_gvec_rotli',
'tcg_gen_gvec_rotri',
'tcg_gen_gvec_sar8v',
'tcg_gen_gvec_sar16v',
'tcg_gen_gvec_sar32v',
@ -3033,6 +3039,8 @@ symbols = (
'tcg_gen_rotl_i64',
'tcg_gen_rotli_i32',
'tcg_gen_rotli_i64',
'tcg_gen_rotli_vec',
'tcg_gen_rotri_vec',
'tcg_gen_rotr_i32',
'tcg_gen_rotr_i64',
'tcg_gen_rotri_i32',
@ -3100,6 +3108,8 @@ symbols = (
'tcg_gen_vec_neg8_i64',
'tcg_gen_vec_neg16_i64',
'tcg_gen_vec_neg32_i64',
'tcg_gen_vec_rotl8i_i64',
'tcg_gen_vec_rotl16i_i64',
'tcg_gen_vec_sar8i_i64',
'tcg_gen_vec_sar16i_i64',
'tcg_gen_vec_shl8i_i64',

10
qemu/m68k.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_m68k
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_m68k
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_m68k
#define helper_gvec_rotl8i helper_gvec_rotl8i_m68k
#define helper_gvec_rotl16i helper_gvec_rotl16i_m68k
#define helper_gvec_rotl32i helper_gvec_rotl32i_m68k
#define helper_gvec_rotl64i helper_gvec_rotl64i_m68k
#define helper_gvec_sar8i helper_gvec_sar8i_m68k
#define helper_gvec_sar8v helper_gvec_sar8v_m68k
#define helper_gvec_sar16i helper_gvec_sar16i_m68k
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_m68k
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_m68k
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_m68k
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_m68k
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_m68k
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_m68k
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_m68k
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_m68k
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_m68k
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_m68k
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_m68k
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_m68k
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_m68k
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_m68k
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_m68k
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_m68k
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_m68k
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_m68k
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_m68k
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_m68k
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_m68k
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_m68k
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_m68k
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_m68k

10
qemu/mips.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips
#define helper_gvec_rotl8i helper_gvec_rotl8i_mips
#define helper_gvec_rotl16i helper_gvec_rotl16i_mips
#define helper_gvec_rotl32i helper_gvec_rotl32i_mips
#define helper_gvec_rotl64i helper_gvec_rotl64i_mips
#define helper_gvec_sar8i helper_gvec_sar8i_mips
#define helper_gvec_sar8v helper_gvec_sar8v_mips
#define helper_gvec_sar16i helper_gvec_sar16i_mips
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_mips
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_mips
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips

10
qemu/mips64.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64
#define helper_gvec_rotl8i helper_gvec_rotl8i_mips64
#define helper_gvec_rotl16i helper_gvec_rotl16i_mips64
#define helper_gvec_rotl32i helper_gvec_rotl32i_mips64
#define helper_gvec_rotl64i helper_gvec_rotl64i_mips64
#define helper_gvec_sar8i helper_gvec_sar8i_mips64
#define helper_gvec_sar8v helper_gvec_sar8v_mips64
#define helper_gvec_sar16i helper_gvec_sar16i_mips64
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips64
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips64
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips64
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips64
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_mips64
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_mips64
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips64
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips64
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips64

10
qemu/mips64el.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64el
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64el
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64el
#define helper_gvec_rotl8i helper_gvec_rotl8i_mips64el
#define helper_gvec_rotl16i helper_gvec_rotl16i_mips64el
#define helper_gvec_rotl32i helper_gvec_rotl32i_mips64el
#define helper_gvec_rotl64i helper_gvec_rotl64i_mips64el
#define helper_gvec_sar8i helper_gvec_sar8i_mips64el
#define helper_gvec_sar8v helper_gvec_sar8v_mips64el
#define helper_gvec_sar16i helper_gvec_sar16i_mips64el
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64el
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips64el
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64el
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips64el
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips64el
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64el
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64el
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64el
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64el
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64el
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64el
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips64el
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips64el
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64el
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64el
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64el
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64el
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64el
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64el
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_mips64el
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_mips64el
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips64el
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips64el
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips64el

10
qemu/mipsel.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mipsel
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mipsel
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mipsel
#define helper_gvec_rotl8i helper_gvec_rotl8i_mipsel
#define helper_gvec_rotl16i helper_gvec_rotl16i_mipsel
#define helper_gvec_rotl32i helper_gvec_rotl32i_mipsel
#define helper_gvec_rotl64i helper_gvec_rotl64i_mipsel
#define helper_gvec_sar8i helper_gvec_sar8i_mipsel
#define helper_gvec_sar8v helper_gvec_sar8v_mipsel
#define helper_gvec_sar16i helper_gvec_sar16i_mipsel
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mipsel
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_mipsel
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_mipsel
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mipsel
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mipsel
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mipsel
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mipsel
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mipsel
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mipsel
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mipsel
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mipsel
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_mipsel
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_mipsel
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mipsel
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mipsel
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mipsel
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mipsel
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mipsel
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mipsel
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_mipsel
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_mipsel
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mipsel
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mipsel
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mipsel

10
qemu/powerpc.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_powerpc
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_powerpc
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_powerpc
#define helper_gvec_rotl8i helper_gvec_rotl8i_powerpc
#define helper_gvec_rotl16i helper_gvec_rotl16i_powerpc
#define helper_gvec_rotl32i helper_gvec_rotl32i_powerpc
#define helper_gvec_rotl64i helper_gvec_rotl64i_powerpc
#define helper_gvec_sar8i helper_gvec_sar8i_powerpc
#define helper_gvec_sar8v helper_gvec_sar8v_powerpc
#define helper_gvec_sar16i helper_gvec_sar16i_powerpc
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_powerpc
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_powerpc
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_powerpc
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_powerpc
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_powerpc
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_powerpc
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_powerpc
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_powerpc
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_powerpc
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_powerpc
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_powerpc
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_powerpc
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_powerpc
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_powerpc
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_powerpc
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_powerpc
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_powerpc
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_powerpc
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_powerpc
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_powerpc
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_powerpc
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_powerpc
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_powerpc
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_powerpc

10
qemu/riscv32.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv32
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv32
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv32
#define helper_gvec_rotl8i helper_gvec_rotl8i_riscv32
#define helper_gvec_rotl16i helper_gvec_rotl16i_riscv32
#define helper_gvec_rotl32i helper_gvec_rotl32i_riscv32
#define helper_gvec_rotl64i helper_gvec_rotl64i_riscv32
#define helper_gvec_sar8i helper_gvec_sar8i_riscv32
#define helper_gvec_sar8v helper_gvec_sar8v_riscv32
#define helper_gvec_sar16i helper_gvec_sar16i_riscv32
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv32
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv32
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv32
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_riscv32
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_riscv32
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv32
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv32
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv32
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_riscv32
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv32
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv32
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_riscv32
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_riscv32
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv32
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv32
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv32
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_riscv32
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_riscv32
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_riscv32
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_riscv32
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_riscv32
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_riscv32
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_riscv32
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_riscv32

10
qemu/riscv64.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv64
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv64
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv64
#define helper_gvec_rotl8i helper_gvec_rotl8i_riscv64
#define helper_gvec_rotl16i helper_gvec_rotl16i_riscv64
#define helper_gvec_rotl32i helper_gvec_rotl32i_riscv64
#define helper_gvec_rotl64i helper_gvec_rotl64i_riscv64
#define helper_gvec_sar8i helper_gvec_sar8i_riscv64
#define helper_gvec_sar8v helper_gvec_sar8v_riscv64
#define helper_gvec_sar16i helper_gvec_sar16i_riscv64
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv64
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv64
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv64
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_riscv64
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_riscv64
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv64
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv64
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv64
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_riscv64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv64
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_riscv64
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_riscv64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv64
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_riscv64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_riscv64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_riscv64
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_riscv64
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_riscv64
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_riscv64
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_riscv64
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_riscv64

10
qemu/sparc.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc
#define helper_gvec_rotl8i helper_gvec_rotl8i_sparc
#define helper_gvec_rotl16i helper_gvec_rotl16i_sparc
#define helper_gvec_rotl32i helper_gvec_rotl32i_sparc
#define helper_gvec_rotl64i helper_gvec_rotl64i_sparc
#define helper_gvec_sar8i helper_gvec_sar8i_sparc
#define helper_gvec_sar8v helper_gvec_sar8v_sparc
#define helper_gvec_sar16i helper_gvec_sar16i_sparc
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_sparc
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_sparc
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_sparc
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_sparc
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_sparc
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_sparc
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_sparc
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_sparc
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_sparc
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_sparc

10
qemu/sparc64.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc64
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc64
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc64
#define helper_gvec_rotl8i helper_gvec_rotl8i_sparc64
#define helper_gvec_rotl16i helper_gvec_rotl16i_sparc64
#define helper_gvec_rotl32i helper_gvec_rotl32i_sparc64
#define helper_gvec_rotl64i helper_gvec_rotl64i_sparc64
#define helper_gvec_sar8i helper_gvec_sar8i_sparc64
#define helper_gvec_sar8v helper_gvec_sar8v_sparc64
#define helper_gvec_sar16i helper_gvec_sar16i_sparc64
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc64
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_sparc64
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc64
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_sparc64
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_sparc64
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc64
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc64
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc64
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc64
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_sparc64
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_sparc64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc64
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc64
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_sparc64
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_sparc64
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_sparc64
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_sparc64
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_sparc64

3
qemu/tcg/README
View file

@ -600,10 +600,11 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
* shri_vec v0, v1, i2
* sari_vec v0, v1, i2
* rotli_vec v0, v1, i2
* shrs_vec v0, v1, s2
* sars_vec v0, v1, s2
Similarly for logical and arithmetic right shift.
Similarly for logical and arithmetic right shift, and left rotate.
* shlv_vec v0, v1, v2

1
qemu/tcg/aarch64/tcg-target.h
View file

@ -133,6 +133,7 @@ typedef enum {
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1

1
qemu/tcg/i386/tcg-target.h
View file

@ -216,6 +216,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2

68
qemu/tcg/tcg-op-gvec.c
View file

@ -2695,6 +2695,74 @@ void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof
}
}
void tcg_gen_vec_rotl8i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
{
uint64_t mask = dup_const(MO_8, 0xff << c);
tcg_gen_shli_i64(s, d, a, c);
tcg_gen_shri_i64(s, a, a, 8 - c);
tcg_gen_andi_i64(s, d, d, mask);
tcg_gen_andi_i64(s, a, a, ~mask);
tcg_gen_or_i64(s, d, d, a);
}
void tcg_gen_vec_rotl16i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
{
uint64_t mask = dup_const(MO_16, 0xffff << c);
tcg_gen_shli_i64(s, d, a, c);
tcg_gen_shri_i64(s, a, a, 16 - c);
tcg_gen_andi_i64(s, d, d, mask);
tcg_gen_andi_i64(s, a, a, ~mask);
tcg_gen_or_i64(s, d, d, a);
}
void tcg_gen_gvec_rotli(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 };
static const GVecGen2i g[4] = {
{ .fni8 = tcg_gen_vec_rotl8i_i64,
.fniv = tcg_gen_rotli_vec,
.fno = gen_helper_gvec_rotl8i,
.opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = tcg_gen_vec_rotl16i_i64,
.fniv = tcg_gen_rotli_vec,
.fno = gen_helper_gvec_rotl16i,
.opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = tcg_gen_rotli_i32,
.fniv = tcg_gen_rotli_vec,
.fno = gen_helper_gvec_rotl32i,
.opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = tcg_gen_rotli_i64,
.fniv = tcg_gen_rotli_vec,
.fno = gen_helper_gvec_rotl64i,
.opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
tcg_debug_assert(vece <= MO_64);
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
if (shift == 0) {
tcg_gen_gvec_mov(s, vece, dofs, aofs, oprsz, maxsz);
} else {
tcg_gen_gvec_2i(s, dofs, aofs, oprsz, maxsz, shift, &g[vece]);
}
}
void tcg_gen_gvec_rotri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz)
{
tcg_debug_assert(vece <= MO_64);
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
tcg_gen_gvec_rotli(s, vece, dofs, aofs, -shift & ((8 << vece) - 1),
oprsz, maxsz);
}
/*
* Specialized generation vector shifts by a non-constant scalar.
*/

6
qemu/tcg/tcg-op-gvec.h
View file

@ -334,6 +334,10 @@ void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_rotli(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_rotri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_shls(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
@ -388,5 +392,7 @@ void tcg_gen_vec_shr8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
void tcg_gen_vec_shr16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
void tcg_gen_vec_sar8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
void tcg_gen_vec_sar16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
void tcg_gen_vec_rotl8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t c);
void tcg_gen_vec_rotl16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t c);
#endif

12
qemu/tcg/tcg-op-vec.c
View file

@ -547,6 +547,18 @@ void tcg_gen_sari_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int6
do_shifti(s, INDEX_op_sari_vec, vece, r, a, i);
}
void tcg_gen_rotli_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
{
do_shifti(s, INDEX_op_rotli_vec, vece, r, a, i);
}
void tcg_gen_rotri_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
{
int bits = 8 << vece;
tcg_debug_assert(i >= 0 && i < bits);
do_shifti(s, INDEX_op_rotli_vec, vece, r, a, -i & (bits - 1));
}
void tcg_gen_cmp_vec(TCGContext *s, TCGCond cond, unsigned vece,
TCGv_vec r, TCGv_vec a, TCGv_vec b)
{

2
qemu/tcg/tcg-op.h
View file

@ -1001,6 +1001,8 @@ void tcg_gen_umax_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_
void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_sari_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_rotli_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_rotri_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
void tcg_gen_shls_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
void tcg_gen_shrs_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);

1
qemu/tcg/tcg-opc.h
View file

@ -245,6 +245,7 @@ DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))

2
qemu/tcg/tcg.c
View file

@ -1078,6 +1078,8 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
return have_vec && TCG_TARGET_HAS_shv_vec;
case INDEX_op_rotli_vec:
return have_vec && TCG_TARGET_HAS_roti_vec;
case INDEX_op_ssadd_vec:
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:

3
qemu/tcg/tcg.h
View file

@ -185,6 +185,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
@ -1091,7 +1092,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s)
}
// UNICORN: Added
#define TCG_OP_DEFS_TABLE_SIZE 185
#define TCG_OP_DEFS_TABLE_SIZE 186
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {

10
qemu/x86_64.h
View file

@ -1234,6 +1234,10 @@
#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_x86_64
#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_x86_64
#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_x86_64
#define helper_gvec_rotl8i helper_gvec_rotl8i_x86_64
#define helper_gvec_rotl16i helper_gvec_rotl16i_x86_64
#define helper_gvec_rotl32i helper_gvec_rotl32i_x86_64
#define helper_gvec_rotl64i helper_gvec_rotl64i_x86_64
#define helper_gvec_sar8i helper_gvec_sar8i_x86_64
#define helper_gvec_sar8v helper_gvec_sar8v_x86_64
#define helper_gvec_sar16i helper_gvec_sar16i_x86_64
@ -2904,6 +2908,8 @@
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_x86_64
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_x86_64
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_x86_64
#define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_x86_64
#define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_x86_64
#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_x86_64
#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_x86_64
#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_x86_64
@ -3027,6 +3033,8 @@
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_x86_64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_x86_64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_x86_64
#define tcg_gen_rotli_vec tcg_gen_rotli_vec_x86_64
#define tcg_gen_rotri_vec tcg_gen_rotri_vec_x86_64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_x86_64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_x86_64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_x86_64
@ -3094,6 +3102,8 @@
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_x86_64
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_x86_64
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_x86_64
#define tcg_gen_vec_rotl8i_i64 tcg_gen_vec_rotl8i_i64_x86_64
#define tcg_gen_vec_rotl16i_i64 tcg_gen_vec_rotl16i_i64_x86_64
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_x86_64
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_x86_64
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_x86_64