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target/arm: Require alignment for load exclusive

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According to the ARM ARM exclusive loads require the same alignment as
exclusive stores. Let's update the memops used for the load to match
that of the store. This adds the alignment requirement to the memops.

Backports commit 4a2fdb78e794c1ad93aa9e160235d6a61a2125de from qemu
This commit is contained in:
Alistair Francis 2018-03-04 01:50:59 -05:00 committed by Lioncash
parent 4a8f556c29
commit 5d742aad0b
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 5 additions and 4 deletions
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9
qemu/target/arm/translate-a64.c
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@ -1906,7 +1906,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
g_assert(size >= 2);
if (size == 2) {
/* The pair must be single-copy atomic for the doubleword. */
memop |= MO_64;
memop |= MO_64 | MO_ALIGN;
tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_exclusive_val, addr, idx, memop);
if (s->be_data == MO_LE) {
tcg_gen_extract_i64(tcg_ctx, cpu_reg(s, rt), tcg_ctx->cpu_exclusive_val, 0, 32);
@ -1916,10 +1916,11 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
tcg_gen_extract_i64(tcg_ctx, cpu_reg(s, rt2), tcg_ctx->cpu_exclusive_val, 0, 32);
}
} else {
/* The pair must be single-copy atomic for *each* doubleword,
but not the entire quadword. */
/* The pair must be single-copy atomic for *each* doubleword, not
the entire quadword, however it must be quadword aligned. */
memop |= MO_64;
tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_exclusive_val, addr, idx, memop);
tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_exclusive_val, addr, idx,
memop | MO_ALIGN_16);
TCGv_i64 addr2 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_addi_i64(tcg_ctx, addr2, addr, 8);