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https://github.com/yuzu-emu/unicorn.git
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target/sparc: Convert to CPUClass::tlb_fill
Backports commit e84942f2ceaa79430414f2cb68d77c044dadca96 from qemu
This commit is contained in:
parent
e98c731550
commit
5d83199931
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@ -5616,8 +5616,8 @@ sparc_symbols = (
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'sparc_cpu_do_interrupt',
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'sparc_cpu_do_unaligned_access',
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'sparc_cpu_get_phys_page_debug',
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'sparc_cpu_handle_mmu_fault',
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'sparc_cpu_register_types',
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'sparc_cpu_tlb_fill',
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'sparc_cpu_unassigned_access',
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'sparc_reg_read',
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'sparc_reg_reset',
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@ -3442,8 +3442,8 @@
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#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc
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#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc
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#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc
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#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc
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#define sparc_cpu_register_types sparc_cpu_register_types_sparc
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#define sparc_cpu_tlb_fill sparc_cpu_tlb_fill_sparc
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#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc
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#define sparc_reg_read sparc_reg_read_sparc
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#define sparc_reg_reset sparc_reg_reset_sparc
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@ -3442,8 +3442,8 @@
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#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc64
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#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc64
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#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc64
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#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc64
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#define sparc_cpu_register_types sparc_cpu_register_types_sparc64
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#define sparc_cpu_tlb_fill sparc_cpu_tlb_fill_sparc64
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#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc64
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#define sparc_reg_read sparc_reg_read_sparc64
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#define sparc_reg_reset sparc_reg_reset_sparc64
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@ -848,9 +848,8 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
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#endif
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cc->set_pc = sparc_cpu_set_pc;
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cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault;
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#else
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cc->tlb_fill = sparc_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->do_unassigned_access = sparc_cpu_unassigned_access;
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cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
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cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
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@ -571,8 +571,9 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
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void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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/* mmu_helper.c */
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int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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int mmu_idx);
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bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
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@ -1930,18 +1930,9 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
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}
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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int ret;
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ret = sparc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
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if (ret) {
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cpu_loop_exit_restore(cs, retaddr);
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}
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sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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@ -25,13 +25,14 @@
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#if defined(CONFIG_USER_ONLY)
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int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
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CPUSPARCState *env = &cpu->env;
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if (rw & 2) {
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = TT_TFAULT;
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} else {
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cs->exception_index = TT_DFAULT;
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@ -41,7 +42,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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env->mmuregs[4] = address;
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#endif
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}
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return 1;
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cpu_loop_exit_restore(cs, retaddr);
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}
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#else
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@ -206,8 +207,9 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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}
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/* Perform address translation */
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int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
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CPUSPARCState *env = &cpu->env;
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@ -216,17 +218,26 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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target_ulong page_size;
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int error_code = 0, prot, access_index;
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/*
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* TODO: If we ever need tlb_vaddr_to_host for this target,
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* then we must figure out how to manipulate FSR and FAR
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* when both MMU_NF and probe are set. In the meantime,
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* do not support this use case.
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*/
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assert(!probe);
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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address, rw, mmu_idx, &page_size);
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address, access_type,
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mmu_idx, &page_size);
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vaddr = address;
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if (error_code == 0) {
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#ifdef DEBUG_MMU
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printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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if (likely(error_code == 0)) {
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qemu_log_mask(CPU_LOG_MMU,
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"Translate at %" VADDR_PRIx " -> "
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TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
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address, paddr, vaddr);
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
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return 0;
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return true;
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}
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if (env->mmuregs[3]) { /* Fault status register */
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@ -242,14 +253,14 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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switching to normal mode. */
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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return true;
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} else {
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if (rw & 2) {
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = TT_TFAULT;
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} else {
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cs->exception_index = TT_DFAULT;
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}
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return 1;
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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@ -713,8 +724,9 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
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}
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/* Perform address translation */
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int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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SPARCCPU *cpu = SPARC_CPU(cs->uc, cs);
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CPUSPARCState *env = &cpu->env;
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@ -725,8 +737,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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address &= TARGET_PAGE_MASK;
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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address, rw, mmu_idx, &page_size);
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if (error_code == 0) {
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address, access_type,
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mmu_idx, &page_size);
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if (likely(error_code == 0)) {
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vaddr = address;
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//trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
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@ -734,10 +747,12 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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// env->dmmu.mmu_secondary_context);
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
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return 0;
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return true;
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}
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/* XXX */
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return 1;
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if (probe) {
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return false;
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}
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cpu_loop_exit_restore(cs, retaddr);
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
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