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cputlb: Move probe_write out of softmmu_template.h
Backports commit 3b08f0a92545ba06fbdeaae929a5172480300c33 from qemu
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@ -516,6 +516,27 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
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victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \
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(ADDR) & TARGET_PAGE_MASK)
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/* Probe for whether the specified guest write access is permitted.
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* If it is not permitted then an exception will be taken in the same
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* way as if this were a real write access (and we will not return).
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* Otherwise the function will return, and there will be a valid
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* entry in the TLB for this access.
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*/
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void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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/* TLB entry is for a different page */
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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}
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}
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#define MMUSUFFIX _mmu
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#define DATA_SIZE 1
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@ -832,29 +832,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
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}
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#endif /* DATA_SIZE > 1 */
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#if DATA_SIZE == 1
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/* Probe for whether the specified guest write access is permitted.
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* If it is not permitted then an exception will be taken in the same
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* way as if this were a real write access (and we will not return).
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* Otherwise the function will return, and there will be a valid
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* entry in the TLB for this access.
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*/
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void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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/* TLB entry is for a different page */
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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}
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}
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#endif
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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