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target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

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The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
for some security issues. Add the definitions for them to be used by named
CPU models.

Backports commit 6c997b4adb300788d61d72e2b8bc67c03a584956 from qemu
This commit is contained in:
Xiaoyao Li 2020-01-14 08:30:08 -05:00 committed by Lioncash
parent 8f275077b0
commit 5e0b249dc0
1 changed files with 8 additions and 5 deletions
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13
qemu/target/i386/cpu.h
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@ -773,12 +773,15 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
/* MSR Feature Bits */
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
#define MSR_ARCH_CAP_SSB_NO (1U << 4)
#define MSR_ARCH_CAP_MDS_NO (1U << 5)
#define MSR_ARCH_CAP_SSB_NO (1U << 4)
#define MSR_ARCH_CAP_MDS_NO (1U << 5)
#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
#define MSR_ARCH_CAP_TAA_NO (1U << 8)
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)