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target/arm: Always pass cacheattr in S1_ptw_translate

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When we changed the interface of get_phys_addr_lpae to require
the cacheattr parameter, this spot was missed. The compiler is
unable to detect the use of NULL vs the nonnull attribute here.

Fixes: 7e98e21c098

Backports commit a6d6f37aed4b171d121cd4a9363fbb41e90dcb53 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 23:40:30 -05:00 committed by Lioncash
parent 40c04c73b0
commit 5e1316a92e
1 changed files with 6 additions and 13 deletions
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19
qemu/target/arm/helper.c
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@ -9959,21 +9959,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
int s2prot;
int ret;
ARMCacheAttrs cacheattrs = {};
ARMCacheAttrs *pcacheattrs = NULL;
if (env->cp15.hcr_el2 & HCR_PTW) {
/*
* PTW means we must fault if this S1 walk touches S2 Device
* memory; otherwise we don't care about the attributes and can
* save the S2 translation the effort of computing them.
*/
pcacheattrs = &cacheattrs;
}
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
false,
&s2pa, &txattrs, &s2prot, &s2size, fi,
pcacheattrs);
&cacheattrs);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@ -9981,8 +9971,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
fi->s1ptw = true;
return ~0;
}
if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
/* Access was to Device memory: generate Permission fault */
if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
/*
* PTW set and S1 walk touched S2 Device memory:
* generate Permission fault.
*/
fi->type = ARMFault_Permission;
fi->s2addr = addr;
fi->stage2 = true;