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target/arm: [tcg] Port to init_disas_context

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Incrementally paves the way towards using the generic instruction translation
loop.

Backports commit 1d8a5535238fc5976e0542a413f4ad88f5d4b233 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-04 19:09:54 -05:00 committed by Lioncash
parent 8581e6f6fe
commit 5e5c722359
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 53 additions and 42 deletions
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95
qemu/target/arm/translate.c
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@ -12032,37 +12032,15 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
return false;
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
static int arm_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cs, int max_insns)
{
TCGContext *tcg_ctx = cs->uc->tcg_ctx;
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong next_page_start;
int max_insns;
bool end_of_page;
TCGContext *tcg_ctx = env->uc->tcg_ctx;
bool block_full = false;
/* generate intermediate code */
/* The A64 decoder has its own top level loop, because it doesn't need
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
gen_intermediate_code_a64(&dc->base, cs, tb);
return;
}
dc->base.tb = tb;
dc->base.pc_first = tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
dc->uc = env->uc;
dc->uc = cs->uc;
dc->pc = dc->base.pc_first;
dc->condjmp = 0;
@ -12072,23 +12050,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
*/
dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3);
dc->thumb = ARM_TBFLAG_THUMB(tb->flags); // qq
dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);
dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags));
dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags);
dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags);
dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE;
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1;
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4;
dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags));
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);
#endif
dc->ns = ARM_TBFLAG_NS(tb->flags);
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);
dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags);
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags);
dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags);
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags);
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags);
dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags);
dc->cp_regs = cpu->cp_regs;
dc->features = env->features;
@ -12107,8 +12085,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
* emit code to generate a software step exception
* end the TB
*/
dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);
dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);
dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags);
dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags);
dc->is_ldex = false;
dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
@ -12120,6 +12098,38 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_ctx->cpu_V1 = tcg_ctx->cpu_F1d;
/* FIXME: tcg_ctx->cpu_M0 can probably be the same as tcg_ctx->cpu_V0. */
tcg_ctx->cpu_M0 = tcg_temp_new_i64(tcg_ctx);
return max_insns;
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
TCGContext *tcg_ctx = cs->uc->tcg_ctx;
CPUARMState *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong next_page_start;
int max_insns;
bool end_of_page;
bool block_full = false;
/* generate intermediate code */
/* The A64 decoder has its own top level loop, because it doesn't need
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
gen_intermediate_code_a64(&dc->base, cs, tb);
return;
}
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
@ -12128,6 +12138,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);
tcg_clear_temp_count();