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tcg/i386: Make direct jump patching thread-safe
Ensure direct jump patching in i386 is atomic by: * naturally aligning a location of direct jump address; * using atomic_read()/atomic_set() for code patching. Backports commit 0d07abf05e98903c7faf204a9a90f7d45b7554dc from qemu
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@ -307,7 +307,7 @@ void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
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static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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/* patch the branch destination */
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stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
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atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
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/* no need to flush icache explicitly */
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}
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#elif defined(__s390x__)
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@ -1149,6 +1149,21 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest)
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tcg_out_branch(s, 0, dest);
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}
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static void tcg_out_nopn(TCGContext *s, int n)
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{
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int i;
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/* Emit 1 or 2 operand size prefixes for the standard one byte nop,
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* "xchg %eax,%eax", forming "xchg %ax,%ax". All cores accept the
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* duplicate prefix, and all of the interesting recent cores can
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* decode and discard the duplicates in a single cycle.
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*/
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tcg_debug_assert(n >= 1);
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for (i = 1; i < n; ++i) {
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tcg_out8(s, 0x66);
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}
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tcg_out8(s, 0x90);
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}
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#if defined(CONFIG_SOFTMMU)
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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@ -1878,6 +1893,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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/* direct jump method */
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int gap;
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/* jump displacement must be aligned for atomic patching;
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* see if we need to add extra nops before jump
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*/
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gap = tcg_pcrel_diff(s, (void*)QEMU_ALIGN_PTR_UP(s->code_ptr + 1, 4));
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if (gap != 1) {
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tcg_out_nopn(s, gap - 1);
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}
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tcg_out8(s, OPC_JMP_long); /* jmp im */
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s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
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tcg_out32(s, 0);
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