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target-arm: Implement fcsel with movcond

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Backports commit 6e061029d74455d83f6fa070ac33de7a356cf60d from qemu
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Richard Henderson 2018-02-11 01:28:57 -05:00 committed by Lioncash
parent 53bd2b1d5c
commit 5ee72ff9f5
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1 changed files with 17 additions and 29 deletions
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46
qemu/target-arm/translate-a64.c
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@ -4207,21 +4207,6 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
} }
} }
/* copy src FP register to dst FP register; type specifies single or double */
static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (type) {
TCGv_i64 v = read_fp_dreg(s, src);
write_fp_dreg(s, dst, v);
tcg_temp_free_i64(tcg_ctx, v);
} else {
TCGv_i32 v = read_fp_sreg(s, src);
write_fp_sreg(s, dst, v);
tcg_temp_free_i32(tcg_ctx, v);
}
}
/* C3.6.24 Floating point conditional select /* C3.6.24 Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+ * +---+---+---+-----------+------+---+------+------+-----+------+------+
@ -4232,7 +4217,8 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned int mos, type, rm, cond, rn, rd; unsigned int mos, type, rm, cond, rn, rd;
TCGLabel *label_continue = NULL; TCGv_i64 t_true, t_false, t_zero;
DisasCompare64 c;
mos = extract32(insn, 29, 3); mos = extract32(insn, 29, 3);
type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
@ -4250,21 +4236,23 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
return; return;
} }
if (cond < 0x0e) { /* not always */ /* Zero extend sreg inputs to 64 bits now. */
TCGLabel *label_match = gen_new_label(tcg_ctx); t_true = tcg_temp_new_i64(tcg_ctx);
label_continue = gen_new_label(tcg_ctx); t_false = tcg_temp_new_i64(tcg_ctx);
arm_gen_test_cc(tcg_ctx, cond, label_match); read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
/* nomatch: */ read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
gen_mov_fp2fp(s, type, rd, rm);
tcg_gen_br(tcg_ctx, label_continue);
gen_set_label(tcg_ctx, label_match);
}
gen_mov_fp2fp(s, type, rd, rn); a64_test_cc(tcg_ctx, &c, cond);
t_zero = tcg_const_i64(tcg_ctx, 0);
tcg_gen_movcond_i64(tcg_ctx, c.cond, t_true, c.value, t_zero, t_true, t_false);
tcg_temp_free_i64(tcg_ctx, t_zero);
tcg_temp_free_i64(tcg_ctx, t_false);
a64_free_cc(tcg_ctx, &c);
if (cond < 0x0e) { /* continue */ /* Note that sregs write back zeros to the high bits,
gen_set_label(tcg_ctx, label_continue); and we've already done the zero-extension. */
} write_fp_dreg(s, rd, t_true);
tcg_temp_free_i64(tcg_ctx, t_true);
} }
/* C3.6.25 Floating-point data-processing (1 source) - single precision */ /* C3.6.25 Floating-point data-processing (1 source) - single precision */