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target-mips: log bad coprocessor0 register accesses with LOG_UNIMP

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Backports commit 965447eecb6b98d6dfc4dbd97f836093c7e398a0 from qemu
This commit is contained in:
Philippe Mathieu-Daudé 2018-03-02 14:12:27 -05:00 committed by Lioncash
parent e7176e6c85
commit 5f78f3cd80
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 6 deletions
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12
qemu/target/mips/translate.c
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@ -4942,7 +4942,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
tcg_gen_movi_tl(s, arg, 0);
}
@ -5015,7 +5015,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
(void)rn; /* avoid a compiler warning */
cp0_unimplemented:
LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
@ -5696,7 +5696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
@ -6362,7 +6362,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
#if defined(TARGET_MIPS64)
@ -6985,7 +6985,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
@ -7645,7 +7645,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
#endif /* TARGET_MIPS64 */