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target/arm/translate-a64: Don't underdecode SIMD ld/st multiple

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In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.

Backports commit e1f220811dbd5d85fb02ff286358f9ee6188938f from qemu
This commit is contained in:
Peter Maydell 2019-02-03 17:36:00 -05:00 committed by Lioncash
parent 80248fecb6
commit 60ccaf56ac
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 1 deletions
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7
qemu/target/arm/translate-a64.c
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@ -3322,6 +3322,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int rm = extract32(insn, 16, 5);
int size = extract32(insn, 10, 2);
int opcode = extract32(insn, 12, 4);
bool is_store = !extract32(insn, 22, 1);
@ -3341,6 +3342,11 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
return;
}
if (!is_postidx && rm != 0) {
unallocated_encoding(s);
return;
}
/* From the shared decode logic */
switch (opcode) {
case 0x0:
@ -3440,7 +3446,6 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
}
if (is_postidx) {
int rm = extract32(insn, 16, 5);
if (rm == 31) {
tcg_gen_mov_i64(tcg_ctx, tcg_rn, tcg_addr);
} else {