yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-07-06 01:20:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Introduce and use read_fp_hreg

Browse source 
Backports commit 3d99d931266eaeaf7e83703a53f32232cd6faad7 from qemu
This commit is contained in:
Richard Henderson 2018-05-15 22:10:50 -04:00 committed by Lioncash
parent 9b42d01480
commit 60dfdb724b
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 15 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

31
qemu/target/arm/translate-a64.c
View file

@ -647,6 +647,15 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
return v; return v;
} }
static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 v = tcg_temp_new_i32(tcg_ctx);
tcg_gen_ld16u_i32(tcg_ctx, v, tcg_ctx->cpu_env, fp_reg_offset(s, reg, MO_16));
return v;
}
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
* If SVE is not enabled, then there are only 128 bits in the vector. * If SVE is not enabled, then there are only 128 bits in the vector.
*/ */
@ -4973,11 +4982,9 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst = NULL; TCGv_ptr fpst = NULL;
TCGv_i32 tcg_op = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
switch (opcode) { switch (opcode) {
case 0x0: /* FMOV */ case 0x0: /* FMOV */
tcg_gen_mov_i32(tcg_ctx, tcg_res, tcg_op); tcg_gen_mov_i32(tcg_ctx, tcg_res, tcg_op);
@ -7908,13 +7915,10 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_ctx, tcg_op2); tcg_temp_free_i64(tcg_ctx, tcg_op2);
tcg_temp_free_i64(tcg_ctx, tcg_res); tcg_temp_free_i64(tcg_ctx, tcg_res);
} else { } else {
TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx); TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx);
read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
gen_helper_neon_mull_s16(tcg_ctx, tcg_res, tcg_op1, tcg_op2); gen_helper_neon_mull_s16(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_res, tcg_res); gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_res, tcg_res);
@ -8459,13 +8463,10 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
fpst = get_fpstatus_ptr(tcg_ctx, true); fpst = get_fpstatus_ptr(tcg_ctx, true);
tcg_op1 = tcg_temp_new_i32(tcg_ctx); tcg_op1 = read_fp_hreg(s, rn);
tcg_op2 = tcg_temp_new_i32(tcg_ctx); tcg_op2 = read_fp_hreg(s, rm);
tcg_res = tcg_temp_new_i32(tcg_ctx); tcg_res = tcg_temp_new_i32(tcg_ctx);
read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
switch (fpopcode) { switch (fpopcode) {
case 0x03: /* FMULX */ case 0x03: /* FMULX */
gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
@ -12389,11 +12390,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
} }
if (is_scalar) { if (is_scalar) {
TCGv_i32 tcg_op = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op = read_fp_hreg(s, rn);
TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
switch (fpop) { switch (fpop) {
case 0x1a: /* FCVTNS */ case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */ case 0x1b: /* FCVTMS */