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arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

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We go with the localised helper.

Backports commit 986950283837f697b35782b9ac3bc99fca614640 from qemu
This commit is contained in:
Alex Bennée 2018-03-08 19:15:05 -05:00 committed by Lioncash
parent 4ea310c131
commit 6102a61b14
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GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 35 additions and 0 deletions
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1
qemu/header_gen.py
View file

@ -3790,6 +3790,7 @@ aarch64_symbols = (
'helper_crc32_64', 'helper_crc32_64',
'helper_crc32c_64', 'helper_crc32c_64',
'helper_fcvtx_f64_to_f32', 'helper_fcvtx_f64_to_f32',
'helper_frecpx_f16',
'helper_frecpx_f32', 'helper_frecpx_f32',
'helper_frecpx_f64', 'helper_frecpx_f64',
'helper_neon_addlp_s16', 'helper_neon_addlp_s16',

29
qemu/target/arm/helper-a64.c
View file

@ -348,6 +348,35 @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
} }
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
{
float_status *fpst = fpstp;
uint16_t val16, sbit;
int16_t exp;
if (float16_is_any_nan(a)) {
float16 nan = a;
if (float16_is_signaling_nan(a, fpst)) {
float_raise(float_flag_invalid, fpst);
nan = float16_maybe_silence_nan(a, fpst);
}
if (fpst->default_nan_mode) {
nan = float16_default_nan(fpst);
}
return nan;
}
val16 = float16_val(a);
sbit = 0x8000 & val16;
exp = extract32(val16, 10, 5);
if (exp == 0) {
return make_float16(deposit32(sbit, 10, 5, 0x1e));
} else {
return make_float16(deposit32(sbit, 10, 5, ~exp));
}
}
float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
{ {
float_status *fpst = fpstp; float_status *fpst = fpstp;

1
qemu/target/arm/helper-a64.h
View file

@ -41,6 +41,7 @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env)
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)

4
qemu/target/arm/translate-a64.c
View file

@ -11468,6 +11468,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
return; return;
case 0x3d: /* FRECPE */ case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
break; break;
case 0x18: /* FRINTN */ case 0x18: /* FRINTN */
need_rmode = true; need_rmode = true;
@ -11591,6 +11592,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3d: /* FRECPE */ case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break; break;
case 0x3f: /* FRECPX */
gen_helper_frecpx_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x5a: /* FCVTNU */ case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */ case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */ case 0x5c: /* FCVTAU */