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target/riscv: Remove manual decoding from gen_store()

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With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Backports commit bce8a342a1f0919479d18ec812b100136daa746b from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 05:05:12 -04:00 committed by Lioncash
parent f91f286ed2
commit 6190837e2f
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 25 additions and 11 deletions
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28
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -175,22 +175,35 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
TCGv dat = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
gen_get_gpr(ctx, dat, a->rs2);
tcg_gen_qemu_st_tl(ctx->uc, dat, t0, ctx->mem_idx, memop);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, dat);
return true;
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm);
return true;
return gen_store(ctx, a, MO_SB);
}
static bool trans_sh(DisasContext *ctx, arg_sh *a)
{
gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm);
return true;
return gen_store(ctx, a, MO_TESW);
}
static bool trans_sw(DisasContext *ctx, arg_sw *a)
{
gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm);
return true;
return gen_store(ctx, a, MO_TESL);
}
#ifdef TARGET_RISCV64
@ -206,8 +219,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm);
return true;
return gen_store(ctx, a, MO_TEQ);
}
#endif

8
qemu/target/riscv/translate.c
View file

@ -57,6 +57,7 @@ typedef struct DisasContext {
struct uc_struct *uc;
} DisasContext;
#ifdef TARGET_RISCV64
/* convert riscv funct3 to qemu memop for load/store */
static const int tcg_memop_lookup[8] = {
[0 ... 7] = -1,
@ -70,6 +71,7 @@ static const int tcg_memop_lookup[8] = {
[6] = MO_TEUL,
#endif
};
#endif
#ifdef TARGET_RISCV64
#define CASE_OP_32_64(X) case X: case glue(X, W)
@ -568,9 +570,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
}
#endif
static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
@ -590,6 +591,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, dat);
}
#endif
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
@ -760,7 +762,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
case 7:
#if defined(TARGET_RISCV64)
/* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2,
gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
GET_C_LD_IMM(ctx->opcode));
#else
/* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/