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target-arm: Add TTBR regime function and use

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Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.

Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
This commit is contained in:
Greg Bellows 2018-02-12 21:29:07 -05:00 committed by Lioncash
parent 5c41e8e7ed
commit 61c9858458
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 19 additions and 5 deletions
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24
qemu/target-arm/helper.c
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@ -4395,6 +4395,21 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
/* Return the TTBR associated with this translation regime */
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
/* TODO: return VTTBR_EL2 */
g_assert_not_reached();
}
if (ttbrn == 0) {
return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
} else {
return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
}
}
/* Return true if the translation regime is using LPAE format page tables */
static inline bool regime_using_lpae_format(CPUARMState *env,
ARMMMUIdx mmu_idx)
@ -4594,7 +4609,6 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
uint32_t *table, uint32_t address)
{
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
int el = regime_el(env, mmu_idx);
TCR *tcr = regime_tcr(env, mmu_idx);
if (address & tcr->mask) {
@ -4602,13 +4616,13 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
/* Translation table walk disabled for TTBR1 */
return false;
}
*table = env->cp15.ttbr1_el[el] & 0xffffc000;
*table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
} else {
if (tcr->raw_tcr & TTBCR_PD0) {
/* Translation table walk disabled for TTBR0 */
return false;
}
*table = env->cp15.ttbr0_el[el] & tcr->base_mask;
*table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
}
*table |= (address >> 18) & 0x3ffc;
return true;
@ -4972,7 +4986,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* we will always flush the TLB any time the ASID is changed).
*/
if (ttbr_select == 0) {
ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0);
ttbr = regime_ttbr(env, mmu_idx, 0);
epd = extract32(tcr->raw_tcr, 7, 1);
tsz = t0sz;
@ -4984,7 +4998,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
granule_sz = 11;
}
} else {
ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1);
ttbr = regime_ttbr(env, mmu_idx, 1);
epd = extract32(tcr->raw_tcr, 23, 1);
tsz = t1sz;