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target-sparc: Use overalignment flags for twinx and block asis

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This allows us to enforce 16 and 64-byte alignment
without any extra overhead.

Backports commit 808832277af11dafee5a55da2b9e41d019b879ca from qemu
This commit is contained in:
Richard Henderson 2018-02-28 11:59:50 -05:00 committed by Lioncash
parent da124da4b1
commit 62ae2a5102
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 9 deletions
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21
qemu/target-sparc/translate.c
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@ -2519,20 +2519,23 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for lddfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
TCGMemOp memop;
TCGv eight;
int i;
gen_check_align(dc, addr, 0x3f);
gen_address_mask(dc, addr);
/* The first operation checks required alignment. */
memop = da.memop | MO_ALIGN_64;
eight = tcg_const_tl(tcg_ctx, 8);
for (i = 0; ; ++i) {
tcg_gen_qemu_ld_i64(dc->uc, tcg_ctx->cpu_fpr[rd / 2 + i], addr,
da.mem_idx, da.memop);
da.mem_idx, memop);
if (i == 7) {
break;
}
tcg_gen_add_tl(tcg_ctx, addr, addr, eight);
memop = da.memop;
}
tcg_temp_free(tcg_ctx, eight);
} else {
@ -2627,20 +2630,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
case GET_ASI_BLOCK:
/* Valid for stdfa on aligned registers only. */
if (size == 8 && (rd & 7) == 0) {
TCGMemOp memop;
TCGv eight;
int i;
gen_check_align(dc, addr, 0x3f);
gen_address_mask(dc, addr);
/* The first operation checks required alignment. */
memop = da.memop | MO_ALIGN_64;
eight = tcg_const_tl(tcg_ctx, 8);
for (i = 0; ; ++i) {
tcg_gen_qemu_st_i64(dc->uc, tcg_ctx->cpu_fpr[rd / 2 + i], addr,
da.mem_idx, da.memop);
da.mem_idx, memop);
if (i == 7) {
break;
}
tcg_gen_add_tl(tcg_ctx, addr, addr, eight);
memop = da.memop;
}
tcg_temp_free(tcg_ctx, eight);
} else {
@ -2699,9 +2705,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
return;
case GET_ASI_DTWINX:
gen_check_align(dc, addr, 15);
gen_address_mask(dc, addr);
tcg_gen_qemu_ld_i64(dc->uc, hi, addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_i64(dc->uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
tcg_gen_qemu_ld_i64(dc->uc, lo, addr, da.mem_idx, da.memop);
break;
@ -2755,9 +2760,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
break;
case GET_ASI_DTWINX:
gen_check_align(dc, addr, 15);
gen_address_mask(dc, addr);
tcg_gen_qemu_st_i64(dc->uc, hi, addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_i64(dc->uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
tcg_gen_qemu_st_i64(dc->uc, lo, addr, da.mem_idx, da.memop);
break;
@ -5650,7 +5654,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
gen_check_align(dc, cpu_addr, 7);
gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
}
break;