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target/arm: Convert VFP VNMLS to decodetree
Convert the VFP VNMLS instruction to decodetree. Backports commit c54a416cc6d60efbc79dd37aaf0c8918c05b5815 from qemu
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parent
67ad40ffa4
commit
638b90de31
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@ -1360,3 +1360,45 @@ static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_sp *a)
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{
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return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
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}
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static void gen_VNMLS_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
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{
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/*
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* VNMLS: -fd + (fn * fm)
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* Note that it isn't valid to replace (-A + B) with (B - A) or similar
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* plausible looking simplifications because this will give wrong results
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* for NaNs.
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*/
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TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
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gen_helper_vfp_muls(tcg_ctx, tmp, vn, vm, fpst);
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gen_helper_vfp_negs(tcg_ctx, vd, vd);
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gen_helper_vfp_adds(tcg_ctx, vd, vd, tmp, fpst);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a)
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{
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return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true);
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}
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static void gen_VNMLS_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
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{
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/*
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* VNMLS: -fd + (fn * fm)
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* Note that it isn't valid to replace (-A + B) with (B - A) or similar
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* plausible looking simplifications because this will give wrong results
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* for NaNs.
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*/
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TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
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gen_helper_vfp_muld(tcg_ctx, tmp, vn, vm, fpst);
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gen_helper_vfp_negd(tcg_ctx, vd, vd);
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gen_helper_vfp_addd(tcg_ctx, vd, vd, tmp, fpst);
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tcg_temp_free_i64(tcg_ctx, tmp);
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}
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static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_sp *a)
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{
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return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
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}
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@ -1449,19 +1449,6 @@ VFP_OP2(div)
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#undef VFP_OP2
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static inline void gen_vfp_F1_mul(DisasContext *s, int dp)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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/* Like gen_vfp_mul() but put result in F1 */
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TCGv_ptr fpst = get_fpstatus_ptr(s, 0);
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if (dp) {
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gen_helper_vfp_muld(tcg_ctx, s->F1d, s->F0d, s->F1d, fpst);
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} else {
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gen_helper_vfp_muls(tcg_ctx, s->F1s, s->F0s, s->F1s, fpst);
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}
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tcg_temp_free_ptr(tcg_ctx, fpst);
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}
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static inline void gen_vfp_F1_neg(DisasContext *s, int dp)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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@ -3240,6 +3227,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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switch (op) {
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case 0:
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case 1:
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case 2:
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/* Already handled by decodetree */
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return 1;
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default:
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@ -3425,16 +3413,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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for (;;) {
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/* Perform the calculation. */
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switch (op) {
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case 2: /* VNMLS: -fd + (fn * fm) */
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/* Note that it isn't valid to replace (-A + B) with (B - A)
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* or similar plausible looking simplifications
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* because this will give wrong results for NaNs.
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*/
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gen_vfp_F1_mul(s, dp);
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gen_mov_F0_vreg(s, dp, rd);
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gen_vfp_neg(s, dp);
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gen_vfp_add(s, dp);
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break;
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case 3: /* VNMLA: -fd + -(fn * fm) */
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gen_vfp_mul(s, dp);
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gen_vfp_F1_neg(s, dp);
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@ -107,3 +107,8 @@ VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp
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VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp
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VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp
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